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公开(公告)号：US20230178648A1
公开(公告)日：2023-06-08
申请号：US17983434
申请日：2022-11-09
Applicant: Richtek Technology Corporation
Inventor： Chih-Wen Hsiung , Wu-Te Weng , Ta-Yung Yang
IPC: H01L29/78 , H01L29/423 , H01L29/66 , H01L29/10
CPC classification number: H01L29/7816 , H01L29/42368 , H01L29/7835 , H01L29/66659 , H01L29/1095
Abstract: An NMOS half-bridge power device includes: a semiconductor layer, a plurality of insulation regions, a first N-type high voltage well and a second N-type high voltage well, which are formed by one same ion implantation process, a first P-type high voltage well and a second P-type high voltage well, which are formed by one same ion implantation process, a first drift oxide region and a second drift oxide region, which are formed by one same etch process including etching a drift oxide layer; a first gate and a second gate, which are formed by one same etch process including etching a poly silicon layer, a first P-type body region and a second P-type body region, which are formed by one same ion implantation process, a first N-type source and a first N-type drain, and a second N-type source and a second N-type drain.
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112.发明公开公开(公告)号：US20230178438A1
公开(公告)日：2023-06-08
申请号：US17981387
申请日：2022-11-05
Applicant: Richtek Technology Corporation
Inventor： Wu-Te Weng , Chih-Wen Hsiung , Ta-Yung Yang
IPC: H01L21/8234
CPC classification number: H01L21/823481 , H01L21/823412 , H01L21/823418 , H01L21/823437 , H01L21/823462
Abstract: An integration manufacturing method of a depletion high voltage NMOS device and a depletion low voltage NMOS device includes: providing a substrate; forming a semiconductor layer on the substrate; forming insulation regions on the semiconductor layer; forming an N-type well in the depletion high voltage NMOS device region; forming a high voltage P-type well in the semiconductor layer, wherein the N-type well and the high voltage P-type well are in contact with each other in a channel direction; forming an oxide layer on the semiconductor layer after the N-type well and the high voltage P-type well formed; forming a low voltage P-type well; and forming an N-type high voltage channel region and an N-type low voltage channel region, such that each of the depletion high voltage NMOS device and the depletion low voltage NMOS device is turned ON when a gate-source voltage thereof is zero voltage.
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公开(公告)号：US20230170262A1
公开(公告)日：2023-06-01
申请号：US17858167
申请日：2022-07-06
Applicant: RICHTEK TECHNOLOGY CORPORATION
Inventor： Chih-Wen Hsiung , Wu-Te Weng , Ta-Yung Yang
IPC: H01L21/8234
CPC classification number: H01L21/823493 , H01L21/823456
Abstract: An integration manufacturing method of a high voltage device and a low voltage device includes: providing a substrate; forming a semiconductor layer on the substrate; forming insulation regions on the semiconductor layer, for defining a high voltage device region and a low voltage device region; forming a first high voltage well in the high voltage device region; forming a second high voltage well in the semiconductor layer, wherein the first high voltage well and the second high voltage well are in contact with each other in a channel direction; forming an oxide layer on the semiconductor layer, wherein the oxide layer overlays the high voltage device region and the low voltage device region; and forming a first low voltage well in the low voltage device region in the semiconductor layer.
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公开(公告)号：US20220407336A1
公开(公告)日：2022-12-22
申请号：US17829394
申请日：2022-06-01
Applicant: Richtek Technology Corporation
Inventor： Wei-Hsu Chang , Ta-Yung Yang
Abstract: A charging control method includes: converting an input power to a DC power; receiving the DC power by a detachable cable to generate a bus power; converting the bus power to a charging power for charging a battery in a charging period; and adjusting the DC power and/or the charging power to track a maximum of a power conversion efficiency; wherein the power conversion efficiency includes one of the following: an input power conversion efficiency, which is a conversion efficiency of converting the input power to the charging power; a DC power conversion efficiency, which is a conversion efficiency of converting the DC power to the charging power; or a bus power conversion efficiency, which is a conversion efficiency of converting the bus power to the charging power.
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公开(公告)号：US20220271676A1
公开(公告)日：2022-08-25
申请号：US17673298
申请日：2022-02-16
Applicant: Richtek Technology Corporation
Inventor： Ta-Yung Yang , Ying-Chieh Su , Yu-Chang Chen
Abstract: A half-bridge flyback power converter: a first transistor, a second transistor and a third transistor which form a half-bridge circuit. The first transistor is turned on for generating a negative circulated current for achieving zero voltage switching of the second transistor. The second transistor is turned on for magnetizing a transformer. The third transistor is turned on during a demagnetized time period to generate an output voltage. The physical size of the first transistor is smaller than physical size of the third transistor.
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Patent Agency Ranking
116.发明申请公开(公告)号：US20220271675A1
公开(公告)日：2022-08-25
申请号：US17673158
申请日：2022-02-16
Applicant: Richtek Technology Corporation
Inventor： Ta-Yung Yang , Ying-Chieh Su , Yu-Chang Chen
Abstract: A flyback power converter includes: a first transistor switching a transformer for generating a primary switching current and an output voltage; and a second transistor generating a circulated current to achieve ZVS (zero voltage switching) of the first transistor; wherein the flyback power converter actively forces at least one switching cycle to be operated in a DCM (discontinuous conduction mode) operation when the primary switching current is determined to have been operating in a non-DCM operation for a predetermined number of switching cycles. The flyback power converter generates a demagnetized signal which emulates the demagnetized time of the transformer for controlling the second transistor during the non-DCM operation. The flyback power converter calibrates the demagnetized signal according to the demagnetized time during the actively fored DCM operation.
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公开(公告)号：US20220239224A1
公开(公告)日：2022-07-28
申请号：US17567130
申请日：2022-01-02
Applicant: RICHTEK TECHNOLOGY CORPORATION
Inventor： Ting-Wei Liao , Chien-Yu Chen , Kun-Huang Yu , Chien-Wei Chiu , Ta-Yung Yang
Abstract: A switching converter circuit for switching one end of an inductor therein between plural voltages according to a pulse width modulation (PWM) signal to convert an input voltage to an output voltage. The switching converter circuit has a driver circuit including a high side driver, a low side driver, a high side sensor circuit, and a low side sensor circuit. The high side sensor circuit is configured to sense a gate-source voltage of a high side metal oxide semiconductor field effect transistor (MOSFET), to generate a low side enable signal for enabling the low side driver to switch a low side MOSFET according to the PWM signal. The low side sensor circuit is configured to sense a gate-source voltage of a low side MOSFET, to generate a high side enable signal for enabling the high side driver to switch a high side MOSFET according to the PWM signal.
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公开(公告)号：US20220239223A1
公开(公告)日：2022-07-28
申请号：US17560761
申请日：2021-12-23
Applicant: RICHTEK TECHNOLOGY CORPORATION
Inventor： Ting-Wei Liao , Chien-Yu Chen , Kun-Huang Yu , Chien-Wei Chiu , Ta-Yung Yang
Abstract: A switching converter circuit, which switches one terminal of an inductor to different voltages, includes a high side MOSFET, a low side MOSFET, and a driver circuit which includes a high side driver, a low side driver, and a dead time control circuit. According to an output current, The dead time control circuit adaptively delays a low side driving signal to generate a high side enable signal for enabling the high side driver to generate a high side driving signal according to a pulse width modulation (PWM) signal; and/or adaptively delays the high side driving signal to generate a low side enable signal for enabling the low side driver to generate the low side driving signal according to the PWM signal, so as to adaptively control a dead time in which the high side MOSFET and the low side MOSFET are both not conductive.
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公开(公告)号：US20220224325A1
公开(公告)日：2022-07-14
申请号：US17568637
申请日：2022-01-04
Applicant: Richtek Technology Corporation
Inventor： Kun-Huang Yu , Chien-Yu Chen , Ting-Wei Liao , Wu-Te Weng , Chien-Wei Chiu , Yong-Zhong Hu , Ta-Yung Yang
IPC: H03K17/16
Abstract: A switch capable of decreasing parasitic inductance includes: a semiconductor device, a first top metal line, and a second top metal line. The second top metal line electrically connects a power supply input end and a current inflow end of the semiconductor device, wherein a first part of the first top metal line is arranged in parallel and adjacent to a second part of the second top metal line. When the semiconductor device is in an ON operation, an input current outflows from the power supply input end, and is divided into a first current and a second current. When the first current and the second current flow through the first part and the second part respectively, the first current and the second current flow opposite to each other, to reduce an total parasitic inductance of the first top metal line and the second top metal line.
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公开(公告)号：US20220223733A1
公开(公告)日：2022-07-14
申请号：US17547707
申请日：2021-12-10
Applicant: Richtek Technology Corporation
Inventor： Chun-Lung Chang , Chih-Wen Hsiung , Kun-Huang Yu , Kuo-Chin Chiu , Wu-Te Weng , Chien-Wei Chiu , Ta-Yung Yang
Abstract: A high voltage device includes: a semiconductor layer, a well region, a shallow trench isolation region, a drift oxide region, a body region, a gate, a source, and a drain. The drift oxide region is located on a drift region. The shallow trench isolation region is located below the drift oxide region. A part of the drift oxide region is located vertically above a part of the shallow trench isolation region and is in contact with the shallow trench isolation region. The shallow trench isolation region is formed between the drain and the body region.
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