公开(公告)号：US20220208785A1

公开(公告)日：2022-06-30

申请号：US17136471

申请日：2020-12-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Monica TITUS ,  Senaka KANAKAMEDALA ,  Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Yao-Sheng LEE

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519

Abstract: An alternating stack of first material layers and second material layers is formed over a substrate. A hard mask layer is formed over the alternating stack. Optionally, an additional hard mask layer can be formed over the hard mask layer. A photoresist layer is applied and patterned, and cavities are formed in the hard mask layer by performing a first anisotropic etch process that transfers a pattern of the openings in the photoresist layer through the hard mask layer. Via openings are formed through an upper portion of the alternating stack by performing a second anisotropic etch process. A cladding liner can be optionally formed on sidewalls of the cavities in the hard mask layer. The via openings can be vertically extend through all layers within the alternating stack by performing a third anisotropic etch process.

公开(公告)号：US20220208600A1

公开(公告)日：2022-06-30

申请号：US17508036

申请日：2021-10-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Roshan Jayakhar TIRUKKONDA ,  Senaka KANAKAMEDALA ,  Raghuveer S. MAKALA ,  Rahul SHARANGPANI ,  Monica TITUS ,  Adarsh RAJASHEKHAR

IPC: H01L21/768 ,  H01L21/306 ,  H01L21/308

Abstract: A source-level semiconductor layer and an alternating stack of first material layers and second material layers is formed above a substrate. A hard mask layer is formed over the alternating stack, and is subsequently patterned to provide a pattern of cavities therethrough. Via openings are formed through the alternating stack by performing an anisotropic etch process. A cladding liner is formed on sidewalls of the cavities in the hard mask layer and on a top surface of the hard mask layer. The via openings are vertically extended at least through the source-level semiconductor layer by performing a second anisotropic etch process employing a combination of the cladding liner and the hard mask layer as an etch mask.

公开(公告)号：US20210408033A1

公开(公告)日：2021-12-30

申请号：US16912279

申请日：2020-06-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Kumar BARASKAR ,  Raghuveer S. MAKALA ,  Peter RABKIN

IPC: H01L27/11582 ,  H01L29/20 ,  H01L29/66 ,  H01L21/28 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L21/02 ,  H01L21/311 ,  H01L21/78

Abstract: A stack including a silicon oxide layer, a germanium-containing layer, and a III-V compound semiconductor layer is formed over a substrate. An alternating stack of insulating layers and spacer material layers is formed over the III-V compound semiconductor layer. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack and into the III-V compound semiconductor layer. Memory opening fill structures including a memory film and a vertical semiconductor channel are formed in the memory openings. The vertical semiconductor channels can include a III-V compound semiconductor channel material that is electrically connected to the III-V compound semiconductor layer. The substrate and at least a portion of the silicon oxide layer can be subsequently detached.

公开(公告)号：US20210408032A1

公开(公告)日：2021-12-30

申请号：US16912196

申请日：2020-06-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Kumar BARASKAR ,  Raghuveer S. MAKALA ,  Peter RABKIN

IPC: H01L27/11582 ,  H01L21/762 ,  H01L27/11556 ,  H01L25/00 ,  H01L25/18 ,  H01L23/00

Abstract: A stack including a silicon oxide layer, a germanium-containing layer, and a III-V compound semiconductor layer is formed over a substrate. An alternating stack of insulating layers and spacer material layers is formed over the III-V compound semiconductor layer. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack and into the III-V compound semiconductor layer. Memory opening fill structures including a memory film and a vertical semiconductor channel are formed in the memory openings. The vertical semiconductor channels can include a III-V compound semiconductor channel material that is electrically connected to the III-V compound semiconductor layer. The substrate and at least a portion of the silicon oxide layer can be subsequently detached.

公开(公告)号：US20210375910A1

公开(公告)日：2021-12-02

申请号：US16887818

申请日：2020-05-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish BARASKAR ,  Peter RABKIN ,  Raghuveer S. MAKALA

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11543 ,  H01L27/11556 ,  H01L29/207 ,  H01L23/522

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and a memory stack structure vertically extending through the alternating stack. The memory stack structure includes a vertical semiconductor channel and a memory film. The vertical semiconductor channel can include a III-V compound semiconductor channel material. A III-V compound substrate semiconductor layer or a III-V compound semiconductor source region can be used to provide low-resistance electrical connection to a bottom end of the vertical semiconductor channel, and a drain region including a graded III-V compound semiconductor material can be used to provide low-resistance electrical connection to a top end of the vertical semiconductor channel.

公开(公告)号：US20210375909A1

公开(公告)日：2021-12-02

申请号：US16887738

申请日：2020-05-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish BARASKAR ,  Peter RABKIN ,  Raghuveer S. MAKALA

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11543 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/207 ,  H01L23/522

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and a memory stack structure vertically extending through the alternating stack. The memory stack structure includes a vertical semiconductor channel and a memory film. The vertical semiconductor channel can include a III-V compound semiconductor channel material. A III-V compound substrate semiconductor layer or a III-V compound semiconductor source region can be used to provide low-resistance electrical connection to a bottom end of the vertical semiconductor channel, and a drain region including a graded III-V compound semiconductor material can be used to provide low-resistance electrical connection to a top end of the vertical semiconductor channel.

公开(公告)号：US20210375908A1

公开(公告)日：2021-12-02

申请号：US16887659

申请日：2020-05-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish BARASKAR ,  Peter RABKIN ,  Raghuveer S. MAKALA

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11543 ,  H01L27/11556 ,  H01L29/207

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and a memory stack structure vertically extending through the alternating stack. The memory stack structure includes a vertical semiconductor channel and a memory film. The vertical semiconductor channel can include a III-V compound semiconductor channel material. A III-V compound substrate semiconductor layer or a III-V compound semiconductor source region can be used to provide low-resistance electrical connection to a bottom end of the vertical semiconductor channel, and a drain region including a graded III-V compound semiconductor material can be used to provide low-resistance electrical connection to a top end of the vertical semiconductor channel.

公开(公告)号：US20210202703A1

公开(公告)日：2021-07-01

申请号：US16728825

申请日：2019-12-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh RAJASHEKHAR ,  Fei ZHOU ,  Raghuveer S. MAKALA ,  Yanli ZHANG ,  Rahul SHARANGPANI

IPC: H01L29/417 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11597

Abstract: A three-dimensional memory device includes an alternating stack of source layers and drain layers located over a substrate, memory openings vertically extending through the alternating stack, vertical word lines located in each one of the memory openings and vertically extending through each of the source layers and the drain layers of the alternating stack, vertical stacks of discrete semiconductor channels located in each one of the memory openings and contacting horizontal surfaces of a respective vertically neighboring pair of a source layer of the source layers and a drain layer of the drain layers, and vertical stacks of discrete memory material portions located in each one of the memory openings and laterally surrounding a respective one of the vertical word lines. Each memory material portion is laterally spaced from a respective one of the semiconductor channels by a respective gate dielectric layer.

公开(公告)号：US20200335516A1

公开(公告)日：2020-10-22

申请号：US16917597

申请日：2020-06-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA ,  Fei ZHOU

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11543 ,  H01L27/11556

Abstract: A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a first single crystalline semiconductor layer, and memory stack structures extending through the alternating stack and containing respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die includes a peripheral circuitry.

公开(公告)号：US20200258896A1

公开(公告)日：2020-08-13

申请号：US16272468

申请日：2019-02-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish BARASKAR ,  Fei ZHOU ,  Ching-Huang LU ,  Raghuveer S. MAKALA

IPC: H01L27/11558 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate, and memory stack structures are formed through the alternating stack. A backside trench is formed through the alternating stack, and backside recesses are formed by removing the sacrificial material layers. An undoped aluminum oxide backside blocking dielectric layer is formed in the backside recesses and on sidewalls the backside trench. A portion of the undoped aluminum oxide backside blocking dielectric layer located at an upper end of the backside trench is converted into a carbon-doped aluminum oxide layer. An electrically conductive material is deposited in the backside recesses and at peripheral regions of the backside trench. The electrically conductive material at the peripheral regions of the backside trench is removed by an etch process, with the carbon-doped aluminum oxide layer providing etch resistivity during the etch process.