公开(公告)号：US20240237343A9

公开(公告)日：2024-07-11

申请号：US18350552

申请日：2023-07-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bing ZHOU ,  Monica TITUS ,  Raghuveer S. MAKALA ,  Rahul SHARANGPANI ,  Senaka KANAKAMEDALA

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: A etch stop structure is formed a sacrificial memory opening fill structure formed within a first-tier memory opening vertically extending through a first-tier alternating stack of first insulating layers and first spacer material layers. The etch stop structure may include a conductive etch stop plate that is formed over a sacrificial memory opening fill material portion inside the first-tier memory opening, or may include a semiconductor plug which is selectively grown from sidewalls of an etch stop semiconductor material layer that is formed over the first-tier alternating stack. A second-tier alternating stack of second insulating layers and second spacer material layers is formed over the first-tier alternating stack and the etch stop structure.

公开(公告)号：US20240138149A1

公开(公告)日：2024-04-25

申请号：US18350552

申请日：2023-07-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bing ZHOU ,  Monica TITUS ,  Raghuveer S. MAKALA ,  Rahul SHARANGPANI ,  Senaka KANAKAMEDALA

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: A etch stop structure is formed a sacrificial memory opening fill structure formed within a first-tier memory opening vertically extending through a first-tier alternating stack of first insulating layers and first spacer material layers. The etch stop structure may include a conductive etch stop plate that is formed over a sacrificial memory opening fill material portion inside the first-tier memory opening, or may include a semiconductor plug which is selectively grown from sidewalls of an etch stop semiconductor material layer that is formed over the first-tier alternating stack. A second-tier alternating stack of second insulating layers and second spacer material layers is formed over the first-tier alternating stack and the etch stop structure.

公开(公告)号：US20180331117A1

公开(公告)日：2018-11-15

申请号：US15593820

申请日：2017-05-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Monica TITUS ,  Zhixin CUI ,  Senaka KANAKAMEDALA ,  Yao-Sheng LEE ,  Chih-Yu LEE

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

Abstract: A joint level dielectric material layer is formed over a first alternating stack of first insulating layers and first spacer material layers. A first memory opening is formed with a tapered sidewall of the joint level dielectric material layer. A second alternating stack of second insulating layers and second spacer material layers is formed over the joint level dielectric material layer. An inter-tier memory opening is formed, which includes a volume of an second memory opening that extends through the second alternating stack and a volume of the first memory opening. A memory film and a semiconductor channel are formed in the inter-tier memory opening with respective tapered portions overlying the tapered sidewall of the joint level dielectric material layer.

公开(公告)号：US20220246517A1

公开(公告)日：2022-08-04

申请号：US17166393

申请日：2021-02-03

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Monica TITUS ,  Ramy Nashed Bassely SAID ,  Rahul SHARANGPANI ,  Senaka KANAKAMEDALA ,  Raghuveer S. MAKALA

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/768

Abstract: A semiconductor structure includes at least one first semiconductor device located on a substrate, lower-level dielectric material layers embedding lower-level metal interconnect structures, at least one second semiconductor device and a dielectric material portion that overlie the lower-level dielectric material layers, at least one upper-level dielectric material layer, and an interconnection via structure vertically extending from the at least one upper-level dielectric material layer to a conductive structure that can be a node of the at least one first semiconductor device or one of lower-level metal interconnect structures. The interconnection via structure includes a transition metal layer and a fluorine-doped filler material portion in contact with the transition metal layer, composed primarily of a filler material selected from a silicide of the transition metal element or aluminum oxide, and including fluorine atoms.

公开(公告)号：US20220208556A1

公开(公告)日：2022-06-30

申请号：US17355955

申请日：2021-06-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Roshan Jayakhar TIRUKKONDA ,  Senaka KANAKAMEDALA ,  Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Monica TITUS

IPC: H01L21/311 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11597 ,  H01L27/11592 ,  H01L21/768

Abstract: An alternating stack of first material layers and second material layers can be formed over a semiconductor material layer. A patterning film is formed over the alternating stack, and openings are formed through the patterning film. Via openings are formed through the alternating stack at least to a top surface of the semiconductor material layer by performing a first anisotropic etch process that transfers a pattern of the openings in the patterning film. A cladding liner can be formed on a top surface of the patterning film and sidewalls of the openings in the pattering film. The via openings can be vertically extended through the semiconductor material layer at least to a bottom surface of the semiconductor material layer by performing a second anisotropic etch process employing the cladding liner as an etch mask.

公开(公告)号：US20220223470A1

公开(公告)日：2022-07-14

申请号：US17657521

申请日：2022-03-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Roshan Jayakhar TIRUKKONDA ,  Monica TITUS ,  Senaka KANAKAMEDALA ,  Raghuveer S. MAKALA ,  Rahul SHARANGPANI ,  Adarsh RAJASHEKAR

IPC: H01L21/768 ,  H01L21/306

Abstract: A method of forming a structure includes forming an alternating stack of first material layers and second material layers over a substrate, forming a mask layer over the alternating stack, forming a cavity in the mask layer, forming a first cladding liner on a sidewall of the cavity in the mask layer, and forming a via opening the alternating stack by performing an anisotropic etch process that transfers a pattern of the cavity in the mask layer through the alternating stack using a combination of the first cladding liner and the mask layer as an etch mask.

公开(公告)号：US20220208788A1

公开(公告)日：2022-06-30

申请号：US17494114

申请日：2021-10-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Katsufumi OKAMOTO ,  Monica TITUS

IPC: H01L27/11582 ,  H01L27/11556

Abstract: An alternating stack of first material layers and second material layers is formed over a substrate. A hard mask layer is formed over the alternating stack and cavities are formed in the hard mask layer. A cladding liner is formed on sidewalls of the cavities in the hard mask layer. Via openings are formed through each layer within the alternating stack by performing an anisotropic etch process that transfers a pattern of the cavities through the alternating stack.

公开(公告)号：US20220208776A1

公开(公告)日：2022-06-30

申请号：US17590278

申请日：2022-02-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Monica TITUS ,  Roshan Jayakhar TIRUKKONDA ,  Senaka KANAKAMEDALA ,  Raghuveer S. MAKALA

IPC: H01L27/1157 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/11519

Abstract: A method includes forming an alternating stack of first and second layers, forming a composite hard mask layer over the alternating stack, forming openings in the hard mask, and forming via openings through the alternating stack by performing an anisotropic etch process that transfers a pattern of the openings in the composite hard mask layer through the alternating stack. The compositing hard mask includes a first cladding material layer which has higher etch resistance than upper and lower patterning films of the composite hard mask.

公开(公告)号：US20240237355A9

公开(公告)日：2024-07-11

申请号：US18350524

申请日：2023-07-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bing ZHOU ,  Monica TITUS ,  Raghuveer S. MAKALA ,  Rahul SHARANGPANI ,  Senaka KANAKAMEDALA

IPC: H10B43/35 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/35 ,  G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27

Abstract: A etch stop structure is formed a sacrificial memory opening fill structure formed within a first-tier memory opening vertically extending through a first-tier alternating stack of first insulating layers and first spacer material layers. The etch stop structure may include a conductive etch stop plate that is formed over a sacrificial memory opening fill material portion inside the first-tier memory opening, or may include a semiconductor plug which is selectively grown from sidewalls of an etch stop semiconductor material layer that is formed over the first-tier alternating stack. A second-tier alternating stack of second insulating layers and second spacer material layers is formed over the first-tier alternating stack and the etch stop structure.

公开(公告)号：US20240138151A1

公开(公告)日：2024-04-25

申请号：US18350524

申请日：2023-07-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bing ZHOU ,  Monica TITUS ,  Raghuveer S. MAKALA ,  Rahul SHARANGPANI ,  Senaka KANAKAMEDALA

IPC: H10B43/35 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/35 ,  G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27

Abstract: A etch stop structure is formed a sacrificial memory opening fill structure formed within a first-tier memory opening vertically extending through a first-tier alternating stack of first insulating layers and first spacer material layers. The etch stop structure may include a conductive etch stop plate that is formed over a sacrificial memory opening fill material portion inside the first-tier memory opening, or may include a semiconductor plug which is selectively grown from sidewalls of an etch stop semiconductor material layer that is formed over the first-tier alternating stack. A second-tier alternating stack of second insulating layers and second spacer material layers is formed over the first-tier alternating stack and the etch stop structure.