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    Non-volatile write buffer data retention pending scheduled verification
    112.
    发明授权
    Non-volatile write buffer data retention pending scheduled verification 有权
    非易失性写入缓冲区数据保留挂起定期验证

    公开(公告)号：US09076530B2

    公开(公告)日：2015-07-07

    申请号：US13762033

    申请日：2013-02-07

    Applicant: Seagate Technology LLC

    Inventor： Kevin Arthur Gomez ,  Ryan James Goss ,  Antoine Khoueir ,  David Scott Ebsen ,  Jon D. Trantham

    IPC: G11C16/06 ,  G11C16/22 ,  G11C11/16 ,  G11C13/00

    CPC classification number: G11C16/06 ,  G11C11/16 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/22 ,  G11C2207/2245

    Abstract: Method and apparatus for managing data in a memory. In accordance with some embodiments, a non-volatile (NV) buffer is adapted to store input write data having a selected logical address. A write circuit is adapted to transfer a copy of the input write data to an NV main memory while retaining the stored input write data in the NV buffer. A verify circuit is adapted to perform a verify operation at the conclusion of a predetermined elapsed time interval to verify successful transfer of the copy of the input write data to the NV main memory. The input write data are retained in the NV buffer until successful transfer is verified.

    Abstract translation: 用于管理存储器中的数据的方法和装置。 根据一些实施例，非易失性（NV）缓冲器适于存储具有选择的逻辑地址的输入写入数据。 写入电路适于将输入写入数据的副本传送到NV主存储器，同时将存储的输入写入数据保留在NV缓冲器中。 验证电路适于在预定经过时间间隔结束时执行验证操作，以验证输入写入数据的副本成功传送到NV主存储器。 输入写入数据保留在NV缓冲器中，直到验证成功传输。

    FORMING A CHARACTERIZATION PARAMETER OF A RESISTIVE MEMORY ELEMENT
    114.
    发明申请
    FORMING A CHARACTERIZATION PARAMETER OF A RESISTIVE MEMORY ELEMENT 有权
    形成电阻记忆元素的特征参数

    公开(公告)号：US20140258646A1

    公开(公告)日：2014-09-11

    申请号：US13789123

    申请日：2013-03-07

    Applicant: SEAGATE TECHNOLOGY LLC

    Inventor： Ryan James Goss ,  Mark Allen Gaertner ,  Antoine Khoueir ,  David Scott Ebsen ,  Jon D. Trantham

    IPC: G06F12/00

    CPC classification number: G11C29/50008 ,  G06F11/10 ,  G06F11/1012 ,  G11C13/00 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0083 ,  G11C2013/0092

    Abstract: An incremental signal is defined that includes at least one of a duration and a peak voltage that is less than a respective minimum programming time or minimum programming voltage step of a resistive memory element. A characterization procedure is repeatedly performed that at least involves: applying a signal to the memory element, the signal being incremented by the incremental signal during each subsequent application; measuring a first resistance of the memory element in response to the signal; and c) measuring a second resistance of the memory element after a time period has elapsed from the measurement of the first resistance with no programming signal applied. In response to the first and second resistance measurements of the characterization procedure, a characterization parameter of the memory element is formed.

    Abstract translation: 定义增量信号，其包括持续时间和峰值电压中的至少一个小于电阻式存储器元件的相应的最小编程时间或最小编程电压阶跃。 重复执行表征过程，其至少包括：将信号施加到存储元件，在每个随后的应用期间，信号由增量信号递增; 响应于所述信号测量所述存储元件的第一电阻; 以及c）在没有施加编程信号的第一电阻的测量经过一段时间之后测量存储元件的第二电阻。 响应于表征过程的第一和第二电阻测量，形成存储元件的表征参数。

    Non-Volatile Write Buffer Data Retention Pending Scheduled Verification
    115.
    发明申请
    Non-Volatile Write Buffer Data Retention Pending Scheduled Verification 有权
    非易失性写入缓冲区数据保留等待定期验证

    公开(公告)号：US20140219034A1

    公开(公告)日：2014-08-07

    申请号：US13762033

    申请日：2013-02-07

    Applicant: SEAGATE TECHNOLOGY LLC

    Inventor： Kevin Arthur Gomez ,  Ryan James Goss ,  Antoine Khoueir ,  David Scott Ebsen ,  Jon D. Trantham

    IPC: G11C16/06

    CPC classification number: G11C16/06 ,  G11C11/16 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/22 ,  G11C2207/2245

    Abstract: Method and apparatus for managing data in a memory. In accordance with some embodiments, a non-volatile (NV) buffer is adapted to store input write data having a selected logical address. A write circuit is adapted to transfer a copy of the input write data to an NV main memory while retaining the stored input write data in the NV buffer. A verify circuit is adapted to perform a verify operation at the conclusion of a predetermined elapsed time interval to verify successful transfer of the copy of the input write data to the NV main memory. The input write data are retained in the NV buffer until successful transfer is verified.

    Abstract translation: 用于管理存储器中的数据的方法和装置。 根据一些实施例，非易失性（NV）缓冲器适于存储具有选择的逻辑地址的输入写入数据。 写入电路适于将输入写入数据的副本传送到NV主存储器，同时将存储的输入写入数据保留在NV缓冲器中。 验证电路适于在预定经过时间间隔结束时执行验证操作，以验证输入写入数据的副本成功传送到NV主存储器。 输入写入数据保留在NV缓冲器中，直到验证成功传输。

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