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    SEMICONDUCTOR DEVICES WITH BACKSIDE CONTACTS AND ISOLATION
    112.
    发明申请
    SEMICONDUCTOR DEVICES WITH BACKSIDE CONTACTS AND ISOLATION 有权

    公开(公告)号：US20220359519A1

    公开(公告)日：2022-11-10

    申请号：US17873858

    申请日：2022-07-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun-Yuan Chen ,  Huan-Chieh Su ,  Cheng-Chi Chuang ,  Chih-Hao Wang

    IPC: H01L27/092 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78

    Abstract: A semiconductor structure includes an isolation structure, a source or drain region over the isolation structure, a channel layer connecting to the source or drain region, a gate structure over the isolation structure and engaging the channel layer, an isolating layer below the channel layer and the gate structure, a dielectric cap below the isolating layer, and a contact structure having a first portion and a second portion. The first portion of the contact structure extends through the isolation structure, and the second portion of the contact structure extends from the first portion of the contact structure, through the dielectric cap and the isolating layer, and to the source or drain region. The first portion of the contact structure is below the second portion and wider than the second portion.

    Dual side contact structures in semiconductor devices
    113.
    发明授权
    Dual side contact structures in semiconductor devices 有权

    公开(公告)号：US11482595B1

    公开(公告)日：2022-10-25

    申请号：US17238983

    申请日：2021-04-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shih-Chuan Chiu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Chih-Hao Wang ,  Huan-Chieh Su ,  Chun-Yuan Chen ,  Li-Zhen Yu ,  Yu-Ming Lin

    IPC: H01L29/06 ,  H01L29/423 ,  H01L21/8234

    Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.

    Semiconductor devices with backside air gap dielectric
    116.
    发明授权
    Semiconductor devices with backside air gap dielectric 有权

    公开(公告)号：US11443987B2

    公开(公告)日：2022-09-13

    申请号：US16888217

    申请日：2020-05-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun-Yuan Chen ,  Huan-Chieh Su ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

    IPC: H01L21/8234 ,  H01L27/088 ,  H01L23/528 ,  H01L21/764 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/417

    Abstract: A method includes providing a structure having transistors, an isolation structure over the transistors, metal plugs through the isolation structure and connecting to the transistors, and a trench with the isolation structure and the metal plugs as sidewalls. The method further includes forming a dielectric liner on the sidewalls of the trench and over the isolation structure and the metal plugs. The dielectric liner is thicker at an opening portion of the trench than at another portion of the trench so that an air gap is formed inside the trench and the air gap is surrounded by the dielectric liner. The method further includes depositing a sacrificial layer over the dielectric liner and over the air gap and performing CMP to remove the sacrificial layer and to recess the dielectric liner until the isolation structure and the metal plugs are exposed. The air gap remains inside the trench.

    Using a liner layer to enlarge process window for a contact via
    117.
    发明授权
    Using a liner layer to enlarge process window for a contact via 有权

    公开(公告)号：US11361986B2

    公开(公告)日：2022-06-14

    申请号：US16808902

    申请日：2020-03-04

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Li-Zhen Yu ,  Cheng-Chi Chuang ,  Chih-Hao Wang ,  Yu-Ming Lin ,  Lin-Yu Huang

    IPC: H01L21/768 ,  H01L23/522 ,  H01L29/66 ,  H01L29/417

    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a substrate, a first contact layer, and a gate electrode. The first contact layer overlies the substrate and the gate electrode overlies the substrate and is laterally spaced from the first contact layer. A first spacer structure surrounds outermost sidewalls of the first contact layer and separates the gate electrode from the first contact layer. A first hard mask structure is arranged over the first contact layer and is between portions of the first spacer structure. A first contact via extends through the first hard mask structure and contacts the first contact layer. A first liner layer is arranged directly between the first hard mask structure and the first spacer structure.

    Backside vias in semiconductor device
    118.
    发明授权
    Backside vias in semiconductor device 有权

    公开(公告)号：US11349004B2

    公开(公告)日：2022-05-31

    申请号：US16984881

    申请日：2020-08-04

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

    IPC: H01L23/528 ,  H01L27/092 ,  H01L23/535 ,  H01L29/417 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/423 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66

    Abstract: Methods of forming backside vias connected to source/drain regions of long-channel semiconductor devices and short-channel semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a second transistor structure adjacent the first transistor structure; a first interconnect structure on a front-side of the first transistor structure and the second transistor structure; and a second interconnect structure on a backside of the first transistor structure and the second transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a second dielectric layer on the backside of the second transistor structure; a first contact extending through the first dielectric layer and electrically coupled to a first source/drain region of the first transistor structure; and a second contact extending through the second dielectric layer and electrically coupled to a second source/drain region of the second transistor structure, the second contact having a second length less than a first length of the first contact.

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