公开(公告)号：US06429045B1

公开(公告)日：2002-08-06

申请号：US09779215

申请日：2001-02-07

Applicant: Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  H. Bernhard Pogge ,  Edmund J. Sprogis ,  Steven H. Voldman

Inventor： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  H. Bernhard Pogge ,  Edmund J. Sprogis ,  Steven H. Voldman

IPC: H01L2144

CPC classification number: H01L29/0657 ,  H01L21/563 ,  H01L23/544 ,  H01L24/81 ,  H01L25/0655 ,  H01L2223/54473 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/81005 ,  H01L2224/81007 ,  H01L2224/81136 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10158 ,  Y10S438/928 ,  H01L2924/00012

Abstract: A technique for fabricating precision aligned macros (PAMs) with reduced risk of electrostatic discharge damage and thermal damage. An electrical and thermal contact is provided through the back of the individual chips to a supporting silicon substrate. A conductive seed layer for electroplating is formed on a support substrate. A dielectric (preferably, a thermid) layer is formed on the seed layer. Vias are formed in the thermid layer and metal contacts are formed in the vias. The front faces of two or more chips are bonded onto the top surface of an alignment substrate, and the chips are aligned to the alignment substrate. The back faces of the chips are bonded to the metal contacts and thermid layer with heat and pressure. The alignment substrate is removed. The front faces of the chips are planarized. Finally, interconnect wiring is formed over the chips and thermid layer.

Abstract translation: 一种制造精密对准宏（PAM）的技术，降低了静电放电损伤和热损伤的风险。 通过单个芯片的背面提供电接触和热接触到支撑硅衬底。 用于电镀的导电种子层形成在支撑衬底上。 在种子层上形成电介质（优选为热）层。 通孔形成在热层中，金属触点形成在通孔中。 将两个以上的芯片的正面接合在取向基板的顶面上，将芯片与取向基板对准。 芯片的背面通过热和压力结合到金属触点和热层。 取出对准基板。 芯片的正面平面化。 最后，在芯片和热层上形成互连布线。

公开(公告)号：US5276641A

公开(公告)日：1994-01-04

申请号：US806027

申请日：1991-12-12

Applicant: Edmund J. Sprogis ,  Hing Wong

Inventor： Edmund J. Sprogis ,  Hing Wong

IPC: G11C11/401 ,  G11C11/4096 ,  G11C11/4097 ,  G11C13/00

CPC classification number: G11C11/4097 ,  G11C11/4096

Abstract: A hybrid open/folded bit line sense amplifier arrangement and accompanying circuitry primarily for use on a ULSI DRAM memory chip to reduce the area needed for a memory cell and eliminate noise between bit lines. The circuitry includes two memory arrays containing a plurality of memory cells interconnected by a plurality of bit lines and word lines. In the preferred embodiment, the memory cells are accessible on every two out of three bit lines encountered by a word line. A set of open bit line sense amplifiers each with two connectors, one multiplexed to a number of bit lines in the first array and the other multiplexed to a number of bit lines in the second array is provided. Each memory array has a set of folded bit line sense amplifiers with two connectors each connector multiplexed to a number of bit lines in the array. The control circuitry with multiplexing ensures that the connectors of the sense amplifiers access only one bit lines at a time. The accessed by the connectors of each folded line sense amplifier are non-adjacent and simultaneously therewith, a connector of an open bit sense amplifier accesses a bit line between the bit lines accessed by the folded sense amplifier. In the preferred embodiment each connector of a sense amplifier is multiplexed to three bit lines. In a second version the connectors are multiplexed to two bit lines.

Abstract translation: 混合的开/折位线读出放大器装置和主要用于ULSI DRAM存储器芯片的相关电路，以减少存储器单元所需的面积并消除位线之间的噪声。 电路包括两个存储器阵列，其包含由多个位线和字线互连的多个存储器单元。 在优选实施例中，存储器单元可以通过字线遇到的三个位线中的每两个进行访问。 提供了一组开放位线读出放大器，每个具有两个连接器，一个复用到第一阵列中的多个位线，另一个复用到第二阵列中的多个位线。 每个存储器阵列具有一组具有两个连接器的折叠位线读出放大器，每个连接器被多路复用到阵列中的多个位线。 具有复用的控制电路确保了读出放大器的连接器一次仅访问一个位线。 由每个折叠线检测放大器的连接器访问的是不相邻的，并且同时，开放位读出放大器的连接器访问由折叠读出放大器访问的位线之间的位线。 在优选实施例中，读出放大器的每个连接器被复用到三个位线。 在第二个版本中，连接器被复用到两个位线。

公开(公告)号：US4801869A

公开(公告)日：1989-01-31

申请号：US42906

申请日：1987-04-27

Applicant: Edmund J. Sprogis

Inventor： Edmund J. Sprogis

IPC: H01L21/66 ,  G01R31/02 ,  G01R31/28 ,  G11C29/24 ,  G01R31/00 ,  G11C7/00

CPC classification number: G01R31/2831 ,  G01R31/024 ,  G01R31/2884 ,  G11C29/24

Abstract: A semiconductor-processing defect monitor construction for diagnosing processing-induced defects. The semiconductor-processing defect monitor utilizes an array layout and includes continuity defect monitoring structures and short-circuit defect monitoring structures. Once a defect has been indicated by a testing operation, the array layout associated with the defect monitor can be used quickly to determine the approximate location of the known defect, thereby facilitating prompt visual observation of the known defect and, thus, prompt determination of the appropriate corrective action to be applied before substantial continued manufacturing has occurred.