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    Hybrid open folded sense amplifier architecture for a memory device
    1.
    发明授权
    Hybrid open folded sense amplifier architecture for a memory device 失效
    用于存储器件的混合开放式折叠式放大器架构

    公开(公告)号：US5276641A

    公开(公告)日：1994-01-04

    申请号：US806027

    申请日：1991-12-12

    Applicant: Edmund J. Sprogis ,  Hing Wong

    Inventor： Edmund J. Sprogis ,  Hing Wong

    IPC: G11C11/401 ,  G11C11/4096 ,  G11C11/4097 ,  G11C13/00

    CPC classification number: G11C11/4097 ,  G11C11/4096

    Abstract: A hybrid open/folded bit line sense amplifier arrangement and accompanying circuitry primarily for use on a ULSI DRAM memory chip to reduce the area needed for a memory cell and eliminate noise between bit lines. The circuitry includes two memory arrays containing a plurality of memory cells interconnected by a plurality of bit lines and word lines. In the preferred embodiment, the memory cells are accessible on every two out of three bit lines encountered by a word line. A set of open bit line sense amplifiers each with two connectors, one multiplexed to a number of bit lines in the first array and the other multiplexed to a number of bit lines in the second array is provided. Each memory array has a set of folded bit line sense amplifiers with two connectors each connector multiplexed to a number of bit lines in the array. The control circuitry with multiplexing ensures that the connectors of the sense amplifiers access only one bit lines at a time. The accessed by the connectors of each folded line sense amplifier are non-adjacent and simultaneously therewith, a connector of an open bit sense amplifier accesses a bit line between the bit lines accessed by the folded sense amplifier. In the preferred embodiment each connector of a sense amplifier is multiplexed to three bit lines. In a second version the connectors are multiplexed to two bit lines.

    Abstract translation: 混合的开/折位线读出放大器装置和主要用于ULSI DRAM存储器芯片的相关电路，以减少存储器单元所需的面积并消除位线之间的噪声。 电路包括两个存储器阵列，其包含由多个位线和字线互连的多个存储器单元。 在优选实施例中，存储器单元可以通过字线遇到的三个位线中的每两个进行访问。 提供了一组开放位线读出放大器，每个具有两个连接器，一个复用到第一阵列中的多个位线，另一个复用到第二阵列中的多个位线。 每个存储器阵列具有一组具有两个连接器的折叠位线读出放大器，每个连接器被多路复用到阵列中的多个位线。 具有复用的控制电路确保了读出放大器的连接器一次仅访问一个位线。 由每个折叠线检测放大器的连接器访问的是不相邻的，并且同时，开放位读出放大器的连接器访问由折叠读出放大器访问的位线之间的位线。 在优选实施例中，读出放大器的每个连接器被复用到三个位线。 在第二个版本中，连接器被复用到两个位线。

    Coil inductor for on-chip or on-chip stack
    3.
    发明授权
    Coil inductor for on-chip or on-chip stack 有权
    用于片上或片上堆叠的线圈电感

    公开(公告)号：US09105627B2

    公开(公告)日：2015-08-11

    申请号：US13289071

    申请日：2011-11-04

    Applicant: Michael J. Shapiro ,  Gary D. Carpenter ,  Alan J. Drake ,  Rachel Gordin ,  Edmund J. Sprogis

    Inventor： Michael J. Shapiro ,  Gary D. Carpenter ,  Alan J. Drake ,  Rachel Gordin ,  Edmund J. Sprogis

    IPC: H01F5/00 ,  H01L27/08 ,  H01L23/498 ,  H01L23/522 ,  H01L23/64 ,  H01L49/02 ,  H01F17/00 ,  H01F41/00

    CPC classification number: H01L23/49822 ,  H01F17/0013 ,  H01F41/005 ,  H01F2017/0086 ,  H01L23/5227 ,  H01L23/645 ,  H01L28/10 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/00

    Abstract: A coil inductor and buck voltage regulator incorporating the coil inductor are provided which can be fabricated on a microelectronic element such as a semiconductor chip, or on an interconnection element such as a semiconductor, glass or ceramic interposer element. When energized, the coil inductor has magnetic flux extending in a direction parallel to first and second opposed surfaces of the microelectronic or interconnection element, and whose peak magnetic flux is disposed between the first and second surfaces. In one example, the coil inductor can be formed by first conductive lines extending along the first surface of the microelectronic or interconnection element, second conductive lines extending along the second surface of the microelectronic or interconnection element, and a plurality of conductive vias, e.g., through silicon vias, extending in direction of a thickness of the microelectronic or interconnection element. A method of making the coil inductor is also provided.

    Abstract translation: 提供了一种结合线圈电感器的线圈电感器和降压稳压器，其可以制造在诸如半导体芯片的微电子元件上，或者在诸如半导体，玻璃或陶瓷插入元件的互连元件上。 当通电时，线圈电感器具有沿平行于微电子或互连元件的第一和第二相对表面的方向延伸的磁通量，并且其峰值磁通量设置在第一和第二表面之间。 在一个示例中，线圈电感器可以由沿着微电子或互连元件的第一表面延伸的第一导线形成，沿着微电子或互连元件的第二表面延伸的第二导电线，以及多个导电通孔， 通过硅通孔，在微电子或互连元件的厚度方向上延伸。 还提供了制造线圈电感器的方法。

    Through wafer vias with dishing correction methods
    7.
    发明授权
    Through wafer vias with dishing correction methods 有权
    通过具有凹陷校正方法的晶片通孔

    公开(公告)号：US08631570B2

    公开(公告)日：2014-01-21

    申请号：US13369414

    申请日：2012-02-09

    Applicant: Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

    Inventor： Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

    IPC: H01K3/10 ,  H05K3/02 ,  H05K3/10 ,  H01L29/40

    CPC classification number: H01L21/76898 ,  H01L21/76838 ,  H01L21/7684 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods of forming through wafer vias (TWVs) and standard contacts in two separate processes to prevent copper first metal layer puddling and shorts are presented. In one embodiment, a method may include forming a TWV into a substrate and a first dielectric layer over the substrate; forming a second dielectric layer over the substrate and the TWV; forming, through the second dielectric layer, at least one contact to the TWV and at least one contact to other structures over the substrate; and forming a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting at least one of the contacts.

    Abstract translation: 提出了通过晶片通孔（TWV）和标准触点在两个单独的工艺中形成以防止铜第一金属层挤压和短路的方法。 在一个实施例中，一种方法可以包括将TWV形成到衬底上并且在衬底上形成第一介电层; 在所述衬底和所述TWV上形成第二电介质层; 通过所述第二电介质层形成至少一个接触到所述TWV和与所述衬底上的其它结构的至少一个接触; 以及在所述第二电介质层上形成第一金属布线层，所述第一金属布线层与所述触点中的至少一个接触。

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