公开(公告)号：US07702011B2

公开(公告)日：2010-04-20

申请号：US11361192

申请日：2006-02-23

申请人： Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Simardeep Maangat ,  Wilson Wong ,  Rakesh Patel

发明人： Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Simardeep Maangat ,  Wilson Wong ,  Rakesh Patel

IPC分类号： H03H7/30

CPC分类号： H04L1/243 ,  H04L25/03878

摘要： Serial data signal receiver circuitry for inclusion on a PLD includes a plurality of equalizer circuits that are connected in series and that are individually controllable so that collectively they can compensate for a wide range of possible input signal attenuation characteristics. Other circuit features may be connected in relation to the equalizer circuits to give the receiver circuitry other capabilities. For example, these other features may include various types of loop-back test circuits, controllable termination resistance, controllable common mode voltage, and a controllable threshold for detection of an input signal. Various aspects of control of the receiver circuitry may be programmable.

摘要翻译： 用于包含在PLD中的串行数据信号接收器电路包括串联连接并且可单独控制的多个均衡器电路，使得它们可以统一地补偿宽范围的可能的输入信号衰减特性。 其他电路特征可以相对于均衡器电路连接以给予接收机电路其他能力。 例如，这些其他特征可以包括各种类型的环回测试电路，可控终端电阻，可控共模电压以及用于检测输入信号的可控阈值。 接收器电路的控制的各个方面可以是可编程的。

公开(公告)号：US20100058099A1

公开(公告)日：2010-03-04

申请号：US12576507

申请日：2009-10-09

申请人： Sergey Shumarayev ,  Bill W. Bereza ,  Chong H. Lee ,  Rakesh H. Patel ,  Wilson Wong

发明人： Sergey Shumarayev ,  Bill W. Bereza ,  Chong H. Lee ,  Rakesh H. Patel ,  Wilson Wong

IPC分类号： G06F1/04 ,  G06F1/12

CPC分类号： H04L5/14 ,  H03K19/17744 ,  H04L27/00

摘要： High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.

摘要翻译： 可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道 达到第二个相对较高的最大数据速率。 相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。 相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。

公开(公告)号：US07622692B2

公开(公告)日：2009-11-24

申请号：US11657018

申请日：2007-01-24

申请人： Glenn Edward McDonald ,  Wilson Wong

发明人： Glenn Edward McDonald ,  Wilson Wong

IPC分类号： G06K9/00

CPC分类号： B07C3/00 ,  Y10S209/90

摘要： Systems and methods for sorting a plurality of unaddressed items may comprise receiving delivery point address data. Furthermore, systems and methods for sorting a plurality of unaddressed items may comprise sorting the plurality of unaddressed items based on the delivery point address data. The plurality of unaddressed items may be sorted in an order in which they are to be delivered within a delivery zone specified by the delivery point address data.

摘要翻译： 用于排序多个未寻址的物品的系统和方法可以包括接收递送点地址数据。 此外，用于排序多个未寻址项目的系统和方法可以包括基于递送点地址数据对多个未寻址项目进行排序。 多个未解决的项目可以按照它们在由递送点地址数据指定的递送区域内被递送的顺序进行排序。

公开(公告)号：US20090284292A1

公开(公告)日：2009-11-19

申请号：US12511024

申请日：2009-07-28

申请人： Wilson Wong ,  Rakesh H. Patel ,  Sergey Shumarayev ,  Tin H. Lai

发明人： Wilson Wong ,  Rakesh H. Patel ,  Sergey Shumarayev ,  Tin H. Lai

IPC分类号： H03K5/12

CPC分类号： H04B7/005 ,  H04L25/03006 ,  H04L25/061

摘要： Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies but not for low frequencies. For low frequency adjustment, the control block controls the normalized signal amplitude in the signal normalization block. In this manner, controlled adjustment for low frequency content is performed in the signal normalization block.

公开(公告)号：US20090257445A1

公开(公告)日：2009-10-15

申请号：US12100360

申请日：2008-04-09

申请人： Allen Chan ,  Sergey Shumarayev ,  Wilson Wong ,  Weiqi Ding

发明人： Allen Chan ,  Sergey Shumarayev ,  Wilson Wong ,  Weiqi Ding

IPC分类号： H04L12/66

CPC分类号： H04L49/30 ,  H04L49/352

摘要： An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes programmable circuitry and 10 Gigabit Ethernet (10 GbE) transceiver circuitry. The programmable circuitry and the transceiver circuitry may be configured to implement the physical (PHY) layer of the 10GbE networking specification. This integrated circuit may then be coupled to an optical transceiver module in order to transmit and receive 10 GbE optical signals. The transceiver circuitry and interface circuitry that connects the transceiver circuitry with the programmable circuitry may be hard-wired or partially hard-wired.

摘要翻译： 集成电路（例如可编程集成电路，例如可编程微控制器，可编程逻辑器件等）包括可编程电路和10千兆以太网（10GbE）收发器电路。 可编程电路和收发器电路可以被配置为实现10GbE网络规范的物理（PHY）层。 该集成电路然后可以耦合到光收发器模块，以便发送和接收10GbE光信号。 将收发器电路与可编程电路连接的收发器电路和接口电路可以是硬接线或部分硬接线的。

公开(公告)号：US07586983B1

公开(公告)日：2009-09-08

申请号：US11510446

申请日：2006-08-24

申请人： Sergey Shumarayev ,  Wilson Wong ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang

发明人： Sergey Shumarayev ,  Wilson Wong ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang

IPC分类号： H03K5/159 ,  H04B1/10

CPC分类号： H04L25/03057

摘要： In high speed receiver circuitry (e.g., on a programmable logic device (PLD) or the like), decision feedback equalization (DFE) circuitry is used to at least partly cancel unwanted offset (e.g., from other elements of the receiver). The data input to the receiver is tristated; and then each DFE tap coefficient is varied in turn to find coefficient values that are associated with transitions between oscillation and non-oscillation of the receiver output signal. The coefficient values found in this way are used to select trial values. If the output signal of the receiver does not oscillate when these trial values are used, the process is repeated starting from these (or subsequent) trial values until a final set of trial values does allow oscillation of the receiver output signal.

摘要翻译： 在高速接收机电路（例如，在可编程逻辑器件（PLD）等上）中，使用判决反馈均衡（DFE）电路来至少部分地消除不期望的偏移（例如，从接收机的其他元件）。 输入到接收机的数据被三态化; 然后依次改变每个DFE抽头系数，以找到与接收机输出信号的振荡和非振荡之间的转换相关联的系数值。 以这种方式找到的系数值用于选择试验值。 如果接收机的输出信号在使用这些试验值时不振荡，则从这些（或后续）试验值开始重复该过程，直到最终的试验值确定允许接收器输出信号的振荡。

公开(公告)号：US07541857B1

公开(公告)日：2009-06-02

申请号：US11323571

申请日：2005-12-29

申请人： Wilson Wong ,  Tin H. Lai ,  Sergey Shumarayev ,  Rakesh H. Patel

发明人： Wilson Wong ,  Tin H. Lai ,  Sergey Shumarayev ,  Rakesh H. Patel

IPC分类号： H03L5/00

CPC分类号： H03F3/45183 ,  H03F3/45632 ,  H03F2203/45212 ,  H03F2203/45646 ,  H03F2203/45681 ,  H03F2203/45702 ,  H03F2203/45726

摘要： An impedance compensation circuit for inputs of a programmable device includes programmable impedance circuits connected with input nodes. The programmable impedance circuits can be configured to apply a compensating voltages to input nodes to reduce or eliminate unwanted offset voltages. An impedance compensation circuit may include resistors in series or current sources in parallel. A set of bypass switches selectively apply each resistor or current source to an input node, thereby changing the offset voltage of the node and compensating for impedance mismatches. Control logic provides signals to control the bypass switches. The control logic may be implemented using programmable device resources, enabling the control logic to be updated and improved after the manufacturing of the device is complete. The control logic can automatically evaluate offset voltages at any time and change compensating impedances accordingly. This reduces manufacturing costs and takes into account temperature and aging effects.

摘要翻译： 用于可编程器件的输入的阻抗补偿电路包括与输入节点连接的可编程阻抗电路。 可编程阻抗电路可以配置为向输入节点施加补偿电压以减少或消除不期望的失调电压。 阻抗补偿电路可以包括并联的串联或电流源的电阻器。 一组旁路开关选择性地将每个电阻器或电流源施加到输入节点，从而改变节点的偏移电压并补偿阻抗失配。 控制逻辑提供信号来控制旁路开关。 可以使用可编程设备资源实现控制逻辑，使得在设备的制造完成之后能够更新和改进控制逻辑。 控制逻辑可以随时自动评估偏移电压，并相应地改变补偿阻抗。 这降低了制造成本并考虑了温度和老化的影响。

公开(公告)号：US07514968B1

公开(公告)日：2009-04-07

申请号：US11786295

申请日：2007-04-10

申请人： Tin H. Lai ,  Wilson Wong ,  Sergey Shumarayev ,  Tim Tri Hoang

发明人： Tin H. Lai ,  Wilson Wong ,  Sergey Shumarayev ,  Tim Tri Hoang

IPC分类号： H03K3/00

CPC分类号： H03K19/018528 ,  H04L25/0272

摘要： An H-tree driver circuit has pull-up and pull-down current sources, each of which is implemented using a low-voltage-cascode topology.

摘要翻译： H-tree驱动电路具有上拉和下拉电流源，每个都使用低压共源共栅拓扑来实现。

公开(公告)号：US07492816B1

公开(公告)日：2009-02-17

申请号：US10853987

申请日：2004-05-25

申请人： Wilson Wong ,  Sergey Shumarayev ,  Rakesh Patel

发明人： Wilson Wong ,  Sergey Shumarayev ,  Rakesh Patel

IPC分类号： H03H7/30

CPC分类号： H04L1/205 ,  H04B17/21 ,  H04B17/24 ,  H04B17/309 ,  H04L25/03006

摘要： A system includes a programmable transmitter device (e.g., a PLD) connected to a programmable receiver device (e.g., another PLD) via a transmission medium for transmitting a high-speed data signal from the transmitter to the receiver. During a test mode of operation a low-speed communication link between the transmitter and receiver allows those devices to work together to transmit test signals having known characteristics from the transmitter to the receiver via the transmission medium, to analyze the test signals as received by the receiver, and to adjust at least some aspect of the system (e.g., equalizer circuitry in the receiver) to at least partly compensate for losses in the test signals as received by the receiver.

摘要翻译： 系统包括经由用于从发射机向接收机发送高速数据信号的传输介质连接到可编程接收机设备（例如，另一个PLD）的可编程发射机设备（例如，PLD）。 在测试操作模式期间，发射机和接收机之间的低速通信链路允许这些设备一起工作，以经由传输介质从发射机向接收机发送具有已知特性的测试信号，以分析由 接收器，并且至少部分地补偿由接收器接收的测试信号中的损耗，系统的至少一些方面（例如，接收机中的均衡器电路）。

公开(公告)号：US07436228B1

公开(公告)日：2008-10-14

申请号：US11317126

申请日：2005-12-22

申请人： Tim Tri Hoang ,  Sergey Shumarayev ,  Wilson Wong

发明人： Tim Tri Hoang ,  Sergey Shumarayev ,  Wilson Wong

IPC分类号： H03K5/00 ,  H03L7/06

CPC分类号： H03L7/087 ,  H03L7/0891 ,  H03L7/093 ,  H03L7/18

摘要： Methods and apparatus are provided for varying the bandwidth of a loop filter in a loop circuit (e.g., a phase-locked loop circuit). The loop filter can include first and second resistor circuitries coupled to a capacitor. One of the resistor circuitries can be coupled to an output of the loop circuit in response to selection of a mode of operation. The resistor circuitries can each include a plurality of resistors that can be selectively coupled in series to the capacitor or bypassed. In addition, the output of the loop circuit can be coupled to a second capacitor. Either or both of the capacitors can be programmable.

摘要翻译： 提供了用于改变环路电路（例如，锁相环电路）中的环路滤波器的带宽的方法和装置。 环路滤波器可以包括耦合到电容器的第一和第二电阻器电路。 响应于操作模式的选择，电阻器电路中的一个可以耦合到环路电路的输出。 电阻器电路可以各自包括可以选择性地串联耦合到电容器或绕过的多个电阻器。 此外，环路电路的输出可以耦合到第二电容器。 电容器中的任一个或两个可以是可编程的。