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    PLD ARCHITECTURE OPTIMIZED FOR 10G ETHERNET PHYSICAL LAYER SOLUTION
    1.
    发明申请
    PLD ARCHITECTURE OPTIMIZED FOR 10G ETHERNET PHYSICAL LAYER SOLUTION 有权
    针对10G以太网物理层解决方案优化的PLD架构

    公开(公告)号：US20090257445A1

    公开(公告)日：2009-10-15

    申请号：US12100360

    申请日：2008-04-09

    申请人： Allen Chan ,  Sergey Shumarayev ,  Wilson Wong ,  Weiqi Ding

    发明人： Allen Chan ,  Sergey Shumarayev ,  Wilson Wong ,  Weiqi Ding

    IPC分类号： H04L12/66

    CPC分类号： H04L49/30 ,  H04L49/352

    摘要： An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes programmable circuitry and 10 Gigabit Ethernet (10 GbE) transceiver circuitry. The programmable circuitry and the transceiver circuitry may be configured to implement the physical (PHY) layer of the 10GbE networking specification. This integrated circuit may then be coupled to an optical transceiver module in order to transmit and receive 10 GbE optical signals. The transceiver circuitry and interface circuitry that connects the transceiver circuitry with the programmable circuitry may be hard-wired or partially hard-wired.

    摘要翻译： 集成电路（例如可编程集成电路，例如可编程微控制器，可编程逻辑器件等）包括可编程电路和10千兆以太网（10GbE）收发器电路。 可编程电路和收发器电路可以被配置为实现10GbE网络规范的物理（PHY）层。 该集成电路然后可以耦合到光收发器模块，以便发送和接收10GbE光信号。 将收发器电路与可编程电路连接的收发器电路和接口电路可以是硬接线或部分硬接线的。

    PLD architecture optimized for 10G Ethernet physical layer solution
    2.
    发明授权
    PLD architecture optimized for 10G Ethernet physical layer solution 有权
    针对10G以太网物理层解决方案优化的PLD架构

    公开(公告)号：US08184651B2

    公开(公告)日：2012-05-22

    申请号：US12100360

    申请日：2008-04-09

    申请人： Allen Chan ,  Sergey Shumarayev ,  Wilson Wong ,  Weiqi Ding

    发明人： Allen Chan ,  Sergey Shumarayev ,  Wilson Wong ,  Weiqi Ding

    IPC分类号： H04L12/56

    CPC分类号： H04L49/30 ,  H04L49/352

    摘要： An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes programmable circuitry and 10 Gigabit Ethernet (10 GbE) transceiver circuitry. The programmable circuitry and the transceiver circuitry may be configured to implement the physical (PHY) layer of the 10 GbE networking specification. This integrated circuit may then be coupled to an optical transceiver module in order to transmit and receive 10 GbE optical signals. The transceiver circuitry and interface circuitry that connects the transceiver circuitry with the programmable circuitry may be hard-wired or partially hard-wired.

    摘要翻译： 集成电路（例如可编程集成电路，例如可编程微控制器，可编程逻辑器件等）包括可编程电路和10千兆以太网（10GbE）收发器电路。 可编程电路和收发器电路可以被配置为实现10GbE网络规范的物理（PHY）层。 该集成电路然后可以耦合到光收发器模块，以便发送和接收10GbE光信号。 将收发器电路与可编程电路连接的收发器电路和接口电路可以是硬接线或部分硬接线的。

    Transmitter with multiple phase locked loops
    3.
    发明授权
    Transmitter with multiple phase locked loops 有权
    具有多个锁相环的变送器

    公开(公告)号：US07821343B1

    公开(公告)日：2010-10-26

    申请号：US12229813

    申请日：2008-08-27

    申请人： Wilson Wong ,  Sergey Shumarayev ,  Allen Chan ,  Weiqi Ding

    发明人： Wilson Wong ,  Sergey Shumarayev ,  Allen Chan ,  Weiqi Ding

    IPC分类号： H03L7/00

    CPC分类号： H03L7/23

    摘要： A transmitter that includes a first phase locked loop (PLL) and a second PLL coupled to the first PLL is described. In one implementation, the first PLL is an inductance-capacitance (LC) type PLL and the second PLL is a ring type PLL. Also, in one embodiment, the transmitter further includes a PLL selection multiplexer coupled to the first and second PLLs, where the PLL selection multiplexer receives an output of the first PLL and an output of the second PLL and outputs either the output of the first PLL or the output of the second PLL. In one implementation, a control signal for controlling selection by the PLL selection multiplexer is programmable at runtime. In one implementation, the transmitter of the present invention further includes a clock generation block coupled to the PLL selection multiplexer, a serializer block coupled to the clock generation block and a transmit driver block coupled to the serializer block. In one embodiment, the transmit driver block includes only one post-tap pre-driver and only one main-tap pre-driver. The transmitter of the present invention is capable of operating in a wide range mode or a low jitter mode by selecting the appropriate PLL. In wide range mode, a wider frequency range is desirable. On the other hand, in low jitter mode, a low jitter is desirable.

    摘要翻译： 描述了包括耦合到第一PLL的第一锁相环（PLL）和第二PLL的发射机。 在一个实现中，第一PLL是电感 - 电容（LC）型PLL，第二PLL是环型PLL。 此外，在一个实施例中，发射机还包括耦合到第一和第二PLL的PLL选择多路复用器，其中PLL选择多路复用器接收第一PLL的输出和第二PLL的输出，并输出第一PLL的输出 或第二PLL的输出。 在一个实现中，用于控制PLL选择多路复用器的选择的控制信号在运行时可编程。 在一个实现中，本发明的发射机还包括耦合到PLL选择多路复用器的时钟产生模块，耦合到时钟产生模块的串行器模块和耦合到串行器模块的发送驱动器模块。 在一个实施例中，发射驱动器块仅包括一个抽头前驱动器和仅一个主抽头预驱动器。 本发明的发射机能够通过选择适当的PLL在宽范围模式或低抖动模式下工作。 在宽范围模式下，需要较宽的频率范围。 另一方面，在低抖动模式中，需要低抖动。

    Signal detect for high-speed serial interface
    4.
    发明授权
    Signal detect for high-speed serial interface 有权
    信号检测用于高速串行接口

    公开(公告)号：US08290750B1

    公开(公告)日：2012-10-16

    申请号：US13036437

    申请日：2011-02-28

    申请人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Weiqi Ding

    发明人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Weiqi Ding

    IPC分类号： H03F1/26

    CPC分类号： H03K5/19 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/1778

    摘要： Signal detection circuitry for a serial interface oversamples the input—i.e., samples the input multiple times per clock cycle—so that the likelihood of missing a signal is reduced. Sampling may be done with a regenerative latch which has a large bandwidth and can latch a signal at high speed. The amplitude threshold for detection may be programmable, particularly in a programmable device. Thus, between the use of a regenerative latch which is likely to catch any signal that might be present, and the use of oversampling to avoid the problem of sampling at the wrong time, the likelihood of failing to detect a signal is greatly diminished. Logic, such as a state machine, may be used to determine whether the samples captured s do or do not represent a signal. That logic may be programmable, allowing a user to set various parameters for signal detection.

    摘要翻译： 串行接口的信号检测电路对输入进行过采样，即每个时钟周期对输入进行多次采样，从而减少信号丢失的可能性。 可以使用具有大带宽的再生锁存器并且可以高速锁存信号来进行采样。 用于检测的幅度阈值可以是可编程的，特别是在可编程器件中。 因此，在可能捕获可能存在的任何信号的再生锁存器的使用之间以及使用过采样以避免在错误时间采样的问题，大大减少了不能检测信号的可能性。 可以使用诸如状态机的逻辑来确定捕获的样本是否或不表示信号。 该逻辑可以是可编程的，允许用户设置用于信号检测的各种参数。

    High-speed serial data signal transmitter driver circuitry
    5.
    发明申请
    High-speed serial data signal transmitter driver circuitry 审中-公开
    高速串行数据信号发射器驱动电路

    公开(公告)号：US20090154591A1

    公开(公告)日：2009-06-18

    申请号：US12002540

    申请日：2007-12-17

    申请人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev ,  Weiqi Ding

    发明人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev ,  Weiqi Ding

    IPC分类号： H04L27/00

    CPC分类号： H04L25/028

    摘要： Transmitter driver circuitry for outputting a high-speed serial data signal (e.g., in the range of about 10 gigabits per second or higher) includes H-tree driver circuitry having only a main driver stage and a post-tap driver stage. At least one transistor in the H-tree driver circuitry is constructed and connected to provide electrostatic discharge protection. PMOS and NMOS current sources are used for the H-tree driver circuitry to enhance power supply noise rejection.

    摘要翻译： 用于输出高速串行数据信号（例如，在大约10吉比特每秒或更高的范围内）的发射器驱动器电路包括仅具有主驱动器级和抽头后驱动级的H树驱动器电路。 H树驱动器电路中的至少一个晶体管被构造和连接以提供静电放电保护。 PMOS和NMOS电流源用于H-tree驱动器电路，以增强电源噪声抑制。

    Signal detect for high-speed serial interface
    7.
    发明授权
    Signal detect for high-speed serial interface 有权
    信号检测用于高速串行接口

    公开(公告)号：US07899649B1

    公开(公告)日：2011-03-01

    申请号：US12053884

    申请日：2008-03-24

    申请人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Weiqi Ding

    发明人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Weiqi Ding

    IPC分类号： G06F19/00

    CPC分类号： H03K5/19 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/1778

    摘要： Signal detection circuitry for a serial interface oversamples the input—i.e., samples the input multiple times per clock cycle—so that the likelihood of missing a signal is reduced. Sampling may be done with a regenerative latch which has a large bandwidth and can latch a signal at high speed. The amplitude threshold for detection may be programmable, particularly in a programmable device. Thus, between the use of a regenerative latch which is likely to catch any signal that might be present, and the use of oversampling to avoid the problem of sampling at the wrong time, the likelihood of failing to detect a signal is greatly diminished. Logic, such as a state machine, may be used to determine whether the samples captured s do or do not represent a signal. That logic may be programmable, allowing a user to set various parameters for signal detection.

    摘要翻译： 串行接口的信号检测电路对输入进行过采样，即每个时钟周期对输入进行多次采样，从而减少信号丢失的可能性。 可以使用具有大带宽的再生锁存器并且可以高速锁存信号来进行采样。 用于检测的幅度阈值可以是可编程的，特别是在可编程器件中。 因此，在可能捕获可能存在的任何信号的再生锁存器的使用之间以及使用过采样以避免在错误时间采样的问题，大大减少了不能检测信号的可能性。 可以使用诸如状态机的逻辑来确定捕获的样本是否或不表示信号。 该逻辑可以是可编程的，允许用户设置用于信号检测的各种参数。

    Apparatus and methods for low-jitter transceiver clocking
    8.
    发明授权
    Apparatus and methods for low-jitter transceiver clocking 有权
    低抖动收发器时钟的装置和方法

    公开(公告)号：US08406258B1

    公开(公告)日：2013-03-26

    申请号：US12752984

    申请日：2010-04-01

    申请人： Wilson Wong ,  Tim Tri Hoang ,  Thungoc M. Tran ,  Sergey Shumarayev ,  Allen Chan

    发明人： Wilson Wong ,  Tim Tri Hoang ,  Thungoc M. Tran ,  Sergey Shumarayev ,  Allen Chan

    IPC分类号： H04J3/06

    CPC分类号： H03M9/00 ,  H03K19/1776 ,  H04J3/047 ,  H04J3/0685

    摘要： One embodiment relates to an integrated circuit which includes multiple communication channels, a clock multiplexer in each channel, two low-jitter clock generator circuits, and clock distribution circuitry. Each channel includes circuitry arranged to communicate a serial data stream using a reference clock signal, and the clock multiplexer in each channel is configured to select the reference clock signal from a plurality of input clock signals. The first low-jitter clock generator circuit is arranged to generate a first clock signal using a first inductor-capacitor-based oscillator circuit, and the second low-jitter clock generator circuit is arranged to generate a second clock signal using a second inductor-capacitor-based oscillator circuit The first and second inductor-capacitor-based oscillator circuits have different tuning ranges. The clock distribution circuitry is arranged to input the first and second low-jitter clock signals to each said clock multiplexer. Other embodiments and features are also disclosed.

    摘要翻译： 一个实施例涉及一种集成电路，其包括多个通信信道，每个信道中的时钟多路复用器，两个低抖动时钟发生器电路和时钟分配电路。 每个通道包括被布置为使用参考时钟信号传送串行数据流的电路，并且每个通道中的时钟复用器被配置为从多个输入时钟信号中选择参考时钟信号。 第一低抖动时钟发生器电路被布置为使用第一基于电感器 - 电容器的振荡器电路产生第一时钟信号，并且第二低抖动时钟发生器电路被布置为使用第二电感器电容器产生第二时钟信号 基振荡电路基于第一和第二电感电容器的振荡电路具有不同的调谐范围。 时钟分配电路被布置为将第一和第二低抖动时钟信号输入到每个所述时钟多路复用器。 还公开了其它实施例和特征。

    Method to digitize analog signals in a system utilizing dynamic analog test multiplexer for diagnostics
    9.
    发明授权
    Method to digitize analog signals in a system utilizing dynamic analog test multiplexer for diagnostics 有权
    使用动态模拟测试多路复用器对系统中的模拟信号进行数字化的方法进行诊断

    公开(公告)号：US08299802B2

    公开(公告)日：2012-10-30

    申请号：US12263290

    申请日：2008-10-31

    申请人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev

    发明人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev

    IPC分类号： G01R31/02

    CPC分类号： G01R31/3167

    摘要： An integrated circuit capable of monitoring analog voltages inside an analog block is presented. The integrated circuit has an analog test multiplexer (mux) whose inputs are connected to analog voltages of interest inside an analog block. The analog test multiplexer directs a selected analog voltage from an analog block to the output of the analog test mux. The integrated circuit further includes an analog monitor state machine which provides the selection bits to the analog test multiplexer, enabling random access to the analog voltages inside the analog block. The integrated circuit also includes an analog to digital converter for converting the selected analog voltage from the analog test multiplexer into a digital representation.

    摘要翻译： 提出了一种能够监视模拟模块内的模拟电压的集成电路。 集成电路具有模拟测试复用器（多路复用器），其输入端连接到模拟模块内的感兴趣的模拟电压。 模拟测试复用器将选定的模拟电压从模拟模块引导到模拟测试复用器的输出。 集成电路还包括模拟监视状态机，其向模拟测试多路复用器提供选择位，使得能够随机访问模拟块内的模拟电压。 集成电路还包括用于将来自模拟测试多路复用器的所选模拟电压转换为数字表示的模数转换器。