公开(公告)号：US10559651B2

公开(公告)日：2020-02-11

申请号：US16114217

申请日：2018-08-28

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Chieh-Te Chen

IPC: H01L21/3213 ,  H01L27/08 ,  H01L49/02 ,  H01L27/108

Abstract: The present invention relates to a method of forming a memory capacitor. A substrate is provided with a plurality of storage node contacts. A patterned supporting structure is formed on the substrate, following by forming a bottom electrode conformally on surface of plural openings in the patterned supporting structure, thereby contacting the storage node contacts. A sacrificial layer is formed in the opening. A soft etching process is performed to remove the bottom electrode on top and partial sidewall of the patterned supporting structure, wherein the soft etching process includes using a fluoride containing compound, a nitrogen and hydrogen containing compound and an oxygen containing compound. The sacrificial layer is completely removed away. A capacitor dielectric layer and a top electrode are formed on the bottom electrode layer.

公开(公告)号：US10529719B2

公开(公告)日：2020-01-07

申请号：US15961827

申请日：2018-04-24

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Po-Han Wu ,  Li-Wei Feng ,  Shih-Han Hung ,  Fu-Che Lee ,  Chien-Cheng Tsai

IPC: H01L27/108 ,  H01L21/768

Abstract: A semiconductor structure includes an active area in a substrate, a device isolation region surrounding the active area, first and second bit line structures on the substrate, a conductive diffusion region in the active area between the first and the second bit line structures, and a contact hole between the first and the second bit line structures. The contact hole partially exposes the conductive diffusion region. A buried plug layer is disposed in the contact hole and in direct contact with the conductive diffusion region. A storage node contact layer is disposed on the buried plug layer within the contact hole. The storage node contact layer has a downwardly protruding portion surrounded by the buried plug layer. The buried plug layer has a U-shaped cross-sectional profile.

公开(公告)号：US20190318929A1

公开(公告)日：2019-10-17

申请号：US15972223

申请日：2018-05-06

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yu-Chen Chuang ,  Fu-Che Lee ,  Ming-Feng Kuo ,  Cheng-Yu Wang ,  Hsien-Shih Chu ,  Li-Chiang Chen

IPC: H01L21/033

Abstract: A patterning method includes the following steps. A hard mask layer is formed on a substrate. Mandrels are formed on the hard mask layer. Mask patterns are formed on the mandrels. Each of the mask patterns is formed on one of the mandrels. Spacers are formed on the hard mask layer. Each of the spacers is formed on a sidewall of one of the mandrels and on a sidewall of one of the mask patterns. A cover layer covering the hard mask layer, the spacers and the mask patterns is formed. A planarization process is performed to remove the cover layer on the mask patterns and the spacer and remove the mask patterns. A part of the cover layer remains between the spacers after the planarization process. The mandrels and the cover layer are removed after the planarization process.

公开(公告)号：US20190295840A1

公开(公告)日：2019-09-26

申请号：US15956722

申请日：2018-04-18

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee

IPC: H01L21/027 ,  H01L21/033 ,  H01L21/768 ,  H01L21/311

Abstract: A patterning method includes the following steps. A mask layer is formed on a material layer. A first hole is formed in the mask layer by a first photolithography process. A first mask pattern is formed in the first hole. A second hole is formed in the mask layer by a second photolithography process. A first spacer is formed on an inner wall of the second hole. A second mask pattern is formed in the second hole after the step of forming the first spacer. The first spacer surrounds the second mask pattern in the second hole. The mask layer and the first spacer are removed. The pattern of the first mask pattern and the second mask pattern are transferred to the material layer by an etching process.

公开(公告)号：US10418367B2

公开(公告)日：2019-09-17

申请号：US16029638

申请日：2018-07-08

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yi-Ching Chang ,  Feng-Yi Chang ,  Fu-Che Lee ,  Chieh-Te Chen

IPC: H01L21/768 ,  H01L27/108

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a cell region and a peripheral region; forming a bit line structure on the cell region and a gate structure on the peripheral region; forming an interlayer dielectric (ILD) layer around the bit line structure and the gate structure; forming a conductive layer on the bit line structure; performing a first photo-etching process to remove part of the conductive layer for forming storage contacts adjacent two sides of the bit line structure and contact plugs adjacent to two sides of the gate structure; forming a first cap layer on the cell region and the peripheral region to cover the bit line structure and the gate structure; and performing a second photo-etching process to remove part of the first cap layer on the cell region.

公开(公告)号：US20190267385A1

公开(公告)日：2019-08-29

申请号：US16406017

申请日：2019-05-08

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Chun-Hsien Lin ,  Fu-Che Lee

IPC: H01L27/108 ,  H01L29/49

Abstract: A method for fabricating a buried word line (BWL) of a dynamic random access memory (DRAM) includes the steps of: forming a first doped region in a substrate; removing part of the first doped region to form a trench in the substrate; forming a gate structure in the trench; and forming a barrier structure between the gate structure and the first doped region.

公开(公告)号：US10373957B2

公开(公告)日：2019-08-06

申请号：US15856084

申请日：2017-12-28

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Yi-Wang Zhan ,  Chieh-Te Chen

IPC: H01L27/108 ,  H01L21/311 ,  H01L21/02 ,  H01L49/02

Abstract: A capacitor structure includes a semiconductor substrate, a dielectric layer disposed on the semiconductor substrate, a storage node pad disposed in the dielectric layer, and a cylindrical lower electrode including a bottom portion recessed into the dielectric layer and in contact with the storage node pad. The bottom extends to a sidewall of the storage node pad.

公开(公告)号：US10366993B2

公开(公告)日：2019-07-30

申请号：US15655909

申请日：2017-07-21

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/49

Abstract: A semiconductor structure includes a semiconductor substrate having a trench isolation region formed therein. A conductive gate electrode is buried in the trench isolation region. An air gap is disposed between the conductive gate electrode and the semiconductor substrate.

公开(公告)号：US10347642B2

公开(公告)日：2019-07-09

申请号：US15856024

申请日：2017-12-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Chien-Ting Ho ,  Shih-Fang Tzou ,  Fu-Che Lee

IPC: H01L21/76 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L29/78 ,  H01L21/28 ,  H01L27/108 ,  H01L21/02

Abstract: A manufacturing method of a semiconductor memory device is provided in the present invention. A cleaning treatment to a storage node contact on a semiconductor substrate is performed, and a metal silicide layer is formed after the cleaning treatment. A gate contact opening penetrating a capping layer of a transistor on the semiconductor substrate is formed after the step of forming the metal silicide layer for exposing a gate structure of the transistor. By the manufacturing method of the semiconductor memory device in the present invention, the gate structure of the transistor may be kept from being influenced and/or damaged by the cleaning treatment of the storage node contact, and the electrical performance of the transistor may be ensured accordingly.

公开(公告)号：US20190189621A1

公开(公告)日：2019-06-20

申请号：US16273057

申请日：2019-02-11

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Chieh-Te Chen

IPC: H01L27/108 ,  H01L21/768

CPC classification number: H01L27/10894 ,  H01L21/7682 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10897

Abstract: The present invention provides a semiconductor device including a semiconductor substrate with a memory cell region and a peripheral region, a gate line in the peripheral region, an etch-stop layer covering the gate line and the semiconductor substrate, a first insulating layer covering the etch-stop layer, two contact plugs disposed on the semiconductor substrate in the peripheral region, two pads disposed on the contact plugs respectively, and a second insulating layer disposed between the pads. The contact plugs are located at two sides of the gate line respectively, and the contact plugs penetrate through the etch-stop layer and the first insulating layer to contact the semiconductor substrate. The second insulating layer is not in contact with the etch-stop layer.