公开(公告)号：US20150140823A1

公开(公告)日：2015-05-21

申请号：US14411931

申请日：2013-09-03

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Jiale Su

IPC: B81C1/00

CPC classification number: B81C1/00396 ,  B81B2203/033 ,  B81C1/00412 ,  B81C1/00619 ,  B81C1/00626 ,  B81C2201/0132 ,  H01L21/3086

Abstract: A silicon etching method of etching a silicon substrate to form silicon trenches having different width dimensions includes: S1, providing a silicon substrate; S2, depositing a mask layer on the silicon substrate; S3, corroding the mask layer to form windows having different width dimensions, wherein a mask layer having a certain thickness is reserved at least at a bottom portion of a window having a non-minimum width dimension, such that all the silicon trenches have the same depth after step S4; and S4, corroding the mask layer at the bottom portion of the window and the silicon substrate to form the silicon trenches. The mask layer having a certain thickness is reserved at the bottom portion of the window having the non-minimum width dimension, a relatively large window is protected, and a relatively small window is etched first, so that the finally obtained silicon trenches have the same depth.

Abstract translation: 蚀刻硅衬底以形成具有不同宽度尺寸的硅沟槽的硅蚀刻方法包括：S1，提供硅衬底; S2，在硅衬底上沉积掩模层; S3，腐蚀掩模层以形成具有不同宽度尺寸的窗口，其中具有一定厚度的掩模层至少在具有非最小宽度尺寸的窗口的底部保留，使得所有硅沟槽具有相同的 步骤S4之后的深度; 和S4，腐蚀窗口底部的掩模层和硅衬底以形成硅沟槽。 具有一定厚度的掩模层被保留在具有非最小宽度尺寸的窗口的底部，相对较大的窗口被保护，并且首先蚀刻相对小的窗口，使得最终获得的硅沟槽具有相同的 深度。

公开(公告)号：US20150118838A1

公开(公告)日：2015-04-30

申请号：US14398849

申请日：2013-05-19

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Shizhen Sun ,  Hao Fang ,  Yong Gu

IPC: H01L27/115 ,  H01L21/28 ,  H01L21/283

CPC classification number: H01L27/1052 ,  H01L21/28273 ,  H01L21/283 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

Abstract: A NOR flash memory and its manufacturing method are provided in the present disclosure, they are in the field of flash memory. In the manufacturing method, a mask dielectric layer is formed on a second polysilicon layer of a gate stack structure. In addition, part of the mask dielectric layer is etched patternedly to expose part of the second polysilicon layer which is close to a source. Furthermore, the exposed second polysilicon layer is self aligned to form a metal silicide layer. Thus in the NOR flash memory, an unetched mask dielectric layer is substantially located between a metal silicide layer and a drain contacting hole of the NOR flash memory. A drain current between the gate electrode and the drain electrode is small, the above manufacturing method is not complex, a process window is large, a side effect is small, which are advantageous to large scale production.

Abstract translation: 在本公开中提供了NOR闪存及其制造方法，它们在闪存的领域中。 在制造方法中，在栅极堆叠结构的第二多晶硅层上形成掩模电介质层。 此外，掩模介电层的一部分被图案化地蚀刻以暴露靠近源极的第二多晶硅层的部分。 此外，暴露的第二多晶硅层自对准以形成金属硅化物层。 因此，在NOR闪速存储器中，未蚀刻的掩模介电层基本上位于NOR闪存的金属硅化物层和漏极接触孔之间。 栅电极和漏电极之间的漏极电流小，上述制造方法不复杂，工艺窗口大，副作用小，有利于大规模生产。

公开(公告)号：US08957494B2

公开(公告)日：2015-02-17

申请号：US14130449

申请日：2012-10-23

Applicant: CSMC Technologies FAB1 Co., Ltd.

Inventor： Lihui Gu

IPC: H01L29/872 ,  H01L29/06 ,  H01L29/66 ,  H01L29/40 ,  H01L29/10

CPC classification number: H01L29/0634 ,  H01L29/0619 ,  H01L29/10 ,  H01L29/402 ,  H01L29/66143 ,  H01L29/872

Abstract: A high-voltage Schottky diode and a manufacturing method thereof are disclosed in the present disclosure. The diode includes: a P-type substrate and two N-type buried layers, a first N-type buried layer is located below a cathode lead-out area, and a second N-type buried layer is located below a cathode region; an epitaxial layer; two N-type well regions located on the epitaxial layer, a first N-type well region is a lateral drift region and it is provided with a cathode lead-out region, and a second N-type well region is located on the second N-type buried layer and it is a cathode region; a first P-type well region located on the second N-type buried layer and surrounding the cathode region; a field oxide isolation region located on the lateral drift region; an anode located on the cathode region and a cathode located on the surface of the cathode lead-out region.

Abstract translation: 公开了一种高电压肖特基二极管及其制造方法。 二极管包括：P型衬底和两个N型埋层，第一N型掩埋层位于阴极引出区下方，第二N型掩埋层位于阴极区下面; 外延层; 位于外延层上的两个N型阱区，第一N型阱区是横向漂移区，并具有阴极引出区，第二N型阱区位于第二N 型埋层，是阴极区; 位于所述第二N型掩埋层上并围绕所述阴极区的第一P型阱区; 位于所述横向漂移区上的场氧化物隔离区; 位于阴极区域的阳极和位于阴极引出区域的表面上的阴极。

公开(公告)号：US08956972B2

公开(公告)日：2015-02-17

申请号：US14351828

申请日：2012-10-12

Applicant: CSMC Technologies Fab1 Co., Ltd.

Inventor： Hsiao-Chia Wu ,  Shilin Fang ,  Tse-Huang Lo ,  Zhengpei Chen ,  Shu Zhang

IPC: H01L21/44 ,  H01L21/768

CPC classification number: H01L21/7685 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/76837 ,  H01L21/76838 ,  H01L24/03

Abstract: A method for manufacturing a semiconductor thick metal structure includes a thick metal deposition step, a metal patterning step, and a passivation step. In the thick metal deposition step, a Ti—TiN laminated structure is used as an anti-reflection layer to implement 4 μm metal etching without residue. In the metal patterning step, N2 is used for the protection of a sidewall to implement on a 4 μm metal concave-convex structure a tilt angle of nearly 90 degrees, and a main over-etching step is added to implement the smoothness of the sidewall of the 4 μm metal concave-convex structure. A half-filled passivation filling structure is used to implement effective passivation protection of 1.5 um metal gaps having less than 4 um of metal thickness. Manufacturing of the 4 μm thick metal structure having a linewidth/gap of 1.5 μm/1.5 μm is finally implemented.

Abstract translation: 一种制造半导体厚金属结构体的方法包括厚金属沉积步骤，金属图案化步骤和钝化步骤。 在厚金属沉积步骤中，使用Ti-TiN层压结构作为抗反射层，以实现无残留的4μm金属蚀刻。 在金属图案化步骤中，使用N 2来保护侧壁以在接近90度的倾斜角度的4μm金属凹凸结构上实施，并且添加主过蚀刻步骤以实现侧壁的平滑度 的4μm金属凹凸结构。 使用半填充钝化填充结构来实现具有小于4μm的金属厚度的1.5um金属间隙的有效钝化保护。 最终实现线宽/间隙为1.5μm/1.5μm的4μm厚的金属结构体的制造。