公开(公告)号：US20020017897A1

公开(公告)日：2002-02-14

申请号：US09978120

申请日：2001-10-15

Applicant: Linear Technology Corporation

Inventor： Milton E. Wilcox ,  Randy G. Flatness

IPC: G05F001/40

CPC classification number: H02M3/156 ,  H02M3/1588 ,  H02M2001/0032 ,  Y02B70/1466 ,  Y02B70/16

Abstract: A circuit and method for controlling a switching voltage regulator having (1) a switch including one or more switching transistors and (2) an output adapted to supply current at a regulated voltage to a load including an output capacitor. The circuit and method generates a control signal to turn said one or more switching transistors OFF under operating conditions when the voltage at the output is capable of being maintained substantially at the regulated voltage by the charge on the output capacitor. Such a circuit and method increases the efficiency of the regulator circuit particularly at low average current levels.

Abstract translation: 一种用于控制开关电压调节器的电路和方法，该开关电压调节器具有（1）包括一个或多个开关晶体管的开关和（2）适于向包括输出电容器的负载提供以调节电压的电流的输出。 该电路和方法产生一个控制信号，以在输出电压能够通过输出电容器上的电荷基本保持在调节电压的工作条件下使所述一个或多个开关晶体管截止。 这种电路和方法特别是在较低的平均电流水平下提高了调节器电路的效率。

公开(公告)号：US20210226535A1

公开(公告)日：2021-07-22

申请号：US17220622

申请日：2021-04-01

Applicant: Linear Technology Corporation

Inventor： Min Chen ,  Bryan Avery Legated

IPC: H02M3/158

Abstract: A peak-buck peak-boost current mode control structure and scheme for a synchronous four-switch and non-synchronous two-switch buck-boost regulators sense input and output voltages to smoothly transition between buck mode, buck-boost mode, and boost mode for high power efficiency and low output ripples. With the inductor current sensing, the control scheme achieves the best performance in continuous conduction and discontinuous condition mode operations.

公开(公告)号：US10595216B2

公开(公告)日：2020-03-17

申请号：US15886754

申请日：2018-02-01

Applicant: Linear Technology Corporation

Inventor： Lance Robert Doherty ,  William Alan Lindsay ,  Jonathan Noah Simon ,  Alain Pierre Levesque

IPC: H04W24/02 ,  H04W24/04 ,  H04W84/18

Abstract: The stability of a channel in a wireless network is evaluated at a node. Upon transmitting a packet from the node on a network channel, a first counter associated with the channel is incremented. Upon receiving an acknowledgment packet responsive to the transmitted packet, a second counter associated with the channel is incremented. A stability metric for the channel is computed based on values stored in the first and second counters. Additionally, interference on a channel of the network is measured at a node. Upon determining that no packet is received during a predetermined time-period on the channel, a received signal strength (RSS) is measured on the channel at an end of the predetermined time-period. Alternatively, upon determining that a packet is received during the predetermined time-period on the channel, the RSS is measured on the channel following completion of the transmission of the packet on the channel.

公开(公告)号：US10534384B2

公开(公告)日：2020-01-14

申请号：US15585399

申请日：2017-05-03

Applicant: Linear Technology Corporation

Inventor： Gregory Manlove ,  James McKenzie ,  Robert Chiacchia ,  Yi Ding Gu ,  Jian Li

IPC: H02M3/156 ,  G05F1/10 ,  G05F1/56 ,  H02M1/32 ,  H02M3/142 ,  H02M3/158 ,  H02M1/00

Abstract: A current mode switching regulator circuit and operating method includes a variable duty cycle power switch controller, a voltage feedback loop that provides a feedback signal based on the output voltage, a current feedback loop that provides a current sense signal based on the output current, and an offset circuit having an external signal input and coupled to the current feedback loop. The power switch controller controls the switching regulator circuit to generate an output voltage and an output current. The offset circuit is configured to provide an offset output control signal, independently of the voltage feedback loop, to control the power switch controller so as to vary a duty cycle of the power switch controller based on the current sense signal and an external offset signal applied to the external signal input.

公开(公告)号：US10313139B2

公开(公告)日：2019-06-04

申请号：US15479187

申请日：2017-04-04

Applicant: Linear Technology Corporation

Inventor： David M. Dwelley ,  Andrew J. Gardner

IPC: H04L12/437 ,  H04L12/10 ,  H04L12/24 ,  G06F1/26 ,  H04B3/44 ,  H04L12/40 ,  H04L12/403 ,  H04L12/44

Abstract: In one embodiment, a master device has a first port and a second port and initially applies a DC voltage only to the first port. A plurality of slave devices, each have a third port and a fourth port, are serially connected to the master device in a ring, via conductors, starting at the first port and ending at the second port. The conductors simultaneously carry the DC voltage and differential data. Each slave device, after performing a detection routine, then sequentially applies the DC voltage to the adjacent downstream slave device in a first direction around the ring. If the master does not detect the presence of the DC voltage at its second port, the master device applies the DC voltage to both the first port and the second port to sequentially power up the slave devices in both directions around the ring of slave devices.

公开(公告)号：US10218394B2

公开(公告)日：2019-02-26

申请号：US15834047

申请日：2017-12-06

Applicant: LINEAR TECHNOLOGY CORPORATION

Inventor： Michael Thomas Engelhardt

IPC: H03K17/30 ,  H04B1/04 ,  H04B15/04 ,  H03H11/46

Abstract: A method and system of providing an active differential resistor. The active differential resistor includes a diode having a first node and a second node. There is a capacitor coupled in series between the first node of the diode and an input of the active differential resistor. There is a current source coupled across the first node and the second node of the diode and configured to forward bias the diode such that a Johnson-Nyquist noise of the active differential resistor is replaced by a shot noise.

公开(公告)号：US10177580B2

公开(公告)日：2019-01-08

申请号：US15135359

申请日：2016-04-21

Applicant: LINEAR TECHNOLOGY CORPORATION

Inventor： Albert M. Wu

IPC: H01M10/44 ,  H01M10/46 ,  H02J7/00 ,  H02J7/34

Abstract: An energy storage stack balancing circuit may balance a set of serially connected energy storage devices. An electronic switching system may control the delivery of energy into and out of the inductor. A controller may control the electronic switching system so as to cause energy to be transferred: from one of the energy storage devices into the inductor and then out of the inductor and into a different one, a subset, or all of the energy storage devices; or from a subset of the energy storage devices into the inductor and then out of the inductor and into one, a different subset, or all of the energy storage devices; or from all of the energy storage devices into the inductor and then out of the inductor and into one or a subset the energy storage devices.

公开(公告)号：US20180316558A1

公开(公告)日：2018-11-01

申请号：US15963987

申请日：2018-04-26

Applicant: Linear Technology Corporation

Inventor： Alain Pierre LEVESQUE ,  Lance Robert DOHERTY ,  David Ramsay Hanson BACHER ,  Sergey AMUR

IPC: H04L12/24 ,  H04W40/02 ,  H04W76/10 ,  H04L12/751

Abstract: In a wireless mesh network having a known or predetermined physical topology, a network node or access point (AP) may promptly begin operation on the network in response to receiving a network advertisement. In particular, the node or AP can store a network communication schedule and adjust the network communication schedule based on parameter value(s) received in the network advertisement received from the network manager. As a result, the node or AP can begin operating in accordance with a network's communication schedule promptly after receiving the network advertisement by transmitting packets using pairs of communication channels and timeslots assigned thereto in the adjusted communication schedule. The network communication schedule stored by the node or AP can take the form of an algorithm that takes the parameter value(s) received in the network advertisement as input(s) and, when executed by the node or AP, outputs the appropriate adjusted network communication schedule.

公开(公告)号：US10033301B2

公开(公告)日：2018-07-24

申请号：US15407749

申请日：2017-01-17

Applicant: LINEAR TECHNOLOGY CORPORATION

Inventor： Jindong (Henry) Zhang ,  Jian Li

IPC: H02M7/537 ,  H03M1/12 ,  H02M3/158 ,  H02M1/12 ,  H02M1/00 ,  H02M3/156

Abstract: A power interface device includes a main switching converter and an auxiliary switching converter. The main switching converter is coupled to an input terminal and an output terminal and configured to operate at a first switching frequency to source a low frequency current from the input terminal to the output terminal. The auxiliary switching converter is coupled to the input terminal and the output terminal in parallel with the main switching converter and configured to operate at a second and higher switching frequency than the first switching frequency to source a fast transient high frequency current from the input terminal to the output terminal.

公开(公告)号：US10003190B2

公开(公告)日：2018-06-19

申请号：US14300999

申请日：2014-06-10

Applicant: LINEAR TECHNOLOGY CORPORATION

Inventor： Joshua John Simonson ,  David Henry Soo ,  Christopher Bruce Umminger

IPC: H02H9/02 ,  H02H9/00 ,  H03K17/16 ,  H02H3/02

CPC classification number: H02H9/025 ,  H02H3/025 ,  H02H9/001 ,  H02H9/004 ,  H03K17/167

Abstract: A novel system is offered for supplying power from an input node to a load coupled to an output node. The system may have multiple switches coupled between the input node and the output node. One or more limiting circuits may be configured for controlling the switches so as to limit outputs of the switches. For example, the limiting circuits may limit current through the respective switches. One or more timers may set a delay period for indicating a fault condition after the limiting is initiated.