公开(公告)号：US12230628B2

公开(公告)日：2025-02-18

申请号：US18053722

申请日：2022-11-08

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Aurelie Arnaud

IPC: H01L27/07 ,  H01L27/02 ,  H01L21/265 ,  H01L21/266

Abstract: The present disclosure concerns a switching device comprising a first phosphorus-doped silicon layer on top of and in contact with a second arsenic-doped silicon layer. The present disclosure also concerns a method of making a switching device that includes forming a phosphorus-doped silicon layer in an arsenic-doped silicon layer.

公开(公告)号：US12095024B2

公开(公告)日：2024-09-17

申请号：US18335927

申请日：2023-06-15

Applicant: STMicroelectronics (Tours) SAS

Inventor： Séverin Larfaillou ,  Delphine Guy-Bouyssou

IPC: H01M10/052 ,  H01M4/04 ,  H01M4/134 ,  H01M4/1395 ,  H01M4/38 ,  H01M4/40 ,  H01M10/0562 ,  H01M10/0585 ,  H01M10/44

CPC classification number: H01M10/052 ,  H01M4/0445 ,  H01M4/134 ,  H01M4/1395 ,  H01M4/38 ,  H01M4/405 ,  H01M10/0562 ,  H01M10/0585 ,  H01M10/44 ,  H01M4/382

Abstract: A thin-film lithium ion battery includes a negative electrode layer, a positive electrode layer, an electrolyte layer disposed between the positive and negative electrode layers, and a lithium layer with lithium pillars extending therefrom formed in the negative electrode layer adjoining the electrolyte layer.

公开(公告)号：US11881413B2

公开(公告)日：2024-01-23

申请号：US18153929

申请日：2023-01-12

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Michael De Cruz ,  Olivier Ory

IPC: H01L21/4763 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L21/4853 ,  H01L21/56

Abstract: A method for manufacturing electronic chips includes forming, on the side of a first face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed beforehand, metallizations coupling contacts of adjacent integrated circuits to one another. The method further includes forming, on the side of the first face of the substrate, first trenches extending through the first face of the substrate and laterally separating the adjacent integrated circuits. The first trenches extend through the metallizations to form at least a portion of metallizations at each of the adjacent circuits.

公开(公告)号：US11811395B2

公开(公告)日：2023-11-07

申请号：US17466604

申请日：2021-09-03

Applicant: STMicroelectronics (Tours) SAS

Inventor： Romain Pichon ,  Yannick Hague

IPC: H03K17/13 ,  H03K17/76 ,  H03K17/30

CPC classification number: H03K17/136 ,  H03K17/76 ,  H03K17/305

Abstract: A control device includes a triac and a first diode that is series-connected between the triac and a first terminal of the device that is configured to be connected to a cathode gate of a thyristor. A second terminal of the control device is configured to be connected to an anode of the thyristor. The triac has a gate connected to a third terminal of the device that is configured to receive a control signal. The thyristor is a component part of one or more of a rectifying bridge circuit, an in-rush current limiting circuit or a solid-state relay circuit.

公开(公告)号：US11705827B2

公开(公告)日：2023-07-18

申请号：US17888686

申请日：2022-08-16

Applicant: STMicroelectronics (Tours) SAS

Inventor： Yannick Hague ,  Romain Launois

IPC: H02M7/162 ,  H02M1/00 ,  H02M7/06

CPC classification number: H02M7/162 ,  H02M1/0085 ,  H02M7/062

Abstract: A circuit includes two input nodes and two output nodes. A rectifier bridge is coupled to the input and output nodes. The rectifier bridge includes a first and second thyristors and a third thyristor coupled in series with a resistor in series. The series coupled third thyristor and resistor are coupled in parallel with one of the first and second thyristors. The first and second thyristors are controlled off, with the third thyristor controlled on, during start up with resistor functioning as an in in-rush current limiter circuit. In normal rectifying operation mode, the first and second thyristors are controlled on, with the third thyristor controlled off.

公开(公告)号：US20230197835A1

公开(公告)日：2023-06-22

申请号：US18110095

申请日：2023-02-15

Applicant: STMicroelectronics (Tours) SAS

Inventor： Patrick HAUTTECOEUR ,  Vincent CARO

IPC: H01L29/747 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/747 ,  H01L29/0661 ,  H01L29/66386

Abstract: A device includes a semiconductor substrate. A step is formed at a periphery of the semiconductor substrate. A first layer, made of polysilicon doped in oxygen, is deposited on top of and in contact with a first surface of the substrate. This first layer extends at least on a wall and bottom of the step. A second layer, made of glass, is deposited on top of the first layer and the edges of the first layer. The second layer forms a boss between the step and a central area of the device.

公开(公告)号：US20230187118A1

公开(公告)日：2023-06-15

申请号：US18074813

申请日：2022-12-05

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Tours) SAS

Inventor： Ludovic FOURNEAUD ,  Laurent MOINDRON ,  Gregory BOUTELOUP

IPC: H01F27/28 ,  H01F27/02 ,  H01F41/04 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01F27/2804 ,  H01F27/022 ,  H01F41/041 ,  H01L23/3107 ,  H01L23/49822 ,  H01L28/10

Abstract: An integrated circuit device includes at least one inductive component with at least one integrated metal winding that is at least partially embedded in a coating. The coating includes at least one ferromagnetic material. The coating optionally includes a non-magnetic material, for example a dielectric.

公开(公告)号：US20230178380A1

公开(公告)日：2023-06-08

申请号：US18153929

申请日：2023-01-12

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Michael DE CRUZ ,  Olivier ORY

IPC: H01L21/48 ,  H01L21/56

CPC classification number: H01L21/4853 ,  H01L21/56

Abstract: A method for manufacturing electronic chips includes forming, on the side of a first face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed beforehand, metallizations coupling contacts of adjacent integrated circuits to one another. The method further includes forming, on the side of the first face of the substrate, first trenches extending through the first face of the substrate and laterally separating the adjacent integrated circuits. The first trenches extend through the metallizations to form at least a portion of metallizations at each of the adjacent circuits.

公开(公告)号：US11574816B2

公开(公告)日：2023-02-07

申请号：US17104869

申请日：2020-11-25

Applicant: STMicroelectronics (Tours) SAS

Inventor： Michael De Cruz ,  Olivier Ory

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/56

Abstract: A method for manufacturing electronic chips includes forming, on the side of a first face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed beforehand, metallizations coupling contacts of adjacent integrated circuits to one another. The method further includes forming, on the side of the first face of the substrate, first trenches extending through the first face of the substrate and laterally separating the adjacent integrated circuits. The first trenches extend through the metallizations to form at least a portion of metallizations at each of the adjacent circuits.

公开(公告)号：US20220311078A1

公开(公告)日：2022-09-29

申请号：US17839196

申请日：2022-06-13

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Mohamed BOUFNICHEL

IPC: H01M50/209 ,  H01M10/46 ,  H01M10/04 ,  H01M10/42 ,  H01M10/44 ,  H01M50/10 ,  H01M50/116 ,  H01M50/124 ,  H01M50/502

Abstract: The disclosure relates to microbattery devices and assemblies. In an embodiment, a device includes a plurality of microbatteries, a first flexible encapsulation film, and a second flexible encapsulation film. Each of the microbatteries includes a first contact terminal and a second contact terminal spaced apart from one another. The first flexible encapsulation film includes a first conductive layer electrically coupled to the first contact terminal of each of the microbatteries, and a first insulating layer on the first conductive layer. The second flexible encapsulation film includes a second conductive layer electrically coupled to the second contact terminal of each of the microbatteries, and a second insulating layer on the second conductive layer.