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143 条记录 (耗时 0.033 秒)

    Localized biasing for silicon on insulator structures
    121.
    发明授权
    Localized biasing for silicon on insulator structures 有权
    硅绝缘体结构的局部偏置

    公开(公告)号：US08159014B2

    公开(公告)日：2012-04-17

    申请号：US12565294

    申请日：2009-09-23

    申请人： Fernando Gonzalez ,  John K. Zahurak

    发明人： Fernando Gonzalez ,  John K. Zahurak

    IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L27/12

    CPC分类号： H01L21/84 ,  H01L27/0214 ,  H01L27/10858 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A silicon-on-insulator device has a localized biasing structure formed in the insulator layer of the SOI. The localized biasing structure includes a patterned conductor that provides a biasing signal to distinct regions of the silicon layer of the SOI. The conductor is recessed into the insulator layer to provide a substantially planar interface with the silicon layer. The conductor is connected to a bias voltage source. In an embodiment, a plurality of conductor is provided that respectively connected to a plurality of voltage sources. Thus, different regions of the silicon layer are biased by different bias signals.

    摘要翻译： 绝缘体上硅器件具有形成在SOI的绝缘体层中的局部偏置结构。 局部偏置结构包括图案化导体，其向SOI的硅层的不同区域提供偏置信号。 导体凹陷到绝缘体层中以提供与硅层基本平坦的界面。 导体连接到偏置电压源。 在一个实施例中，提供分别连接到多个电压源的多个导体。 因此，硅层的不同区域被不同的偏置信号偏置。

    Localized biasing for silicon on insulator structures
    126.
    发明授权
    Localized biasing for silicon on insulator structures 有权
    硅绝缘体结构的局部偏置

    公开(公告)号：US07608927B2

    公开(公告)日：2009-10-27

    申请号：US10230938

    申请日：2002-08-29

    申请人： Fernando Gonzalez ,  John K. Zahurak

    发明人： Fernando Gonzalez ,  John K. Zahurak

    IPC分类号： H01L23/48

    CPC分类号： H01L21/84 ,  H01L27/0214 ,  H01L27/10858 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A silicon-on-insulator device has a localized biasing structure formed in the insulator layer of the SOI. The localized biasing structure includes a patterned conductor that provides a biasing signal to distinct regions of the silicon layer of the SOI. The conductor is recessed into the insulator layer to provide a substantially planar interface with the silicon layer. The conductor is connected to a bias voltage source. In an embodiment, a plurality of conductor is provided that respectively connected to a plurality of voltage sources. Thus, different regions of the silicon layer are biased by different bias signals.

    摘要翻译： 绝缘体上硅器件具有形成在SOI的绝缘体层中的局部偏置结构。 局部偏置结构包括图案化导体，其向SOI的硅层的不同区域提供偏置信号。 导体凹陷到绝缘体层中以提供与硅层基本平坦的界面。 导体连接到偏置电压源。 在一个实施例中，提供分别连接到多个电压源的多个导体。 因此，硅层的不同区域被不同的偏置信号偏置。

    Methods of forming recessed access devices associated with semiconductor constructions
    127.
    发明授权
    Methods of forming recessed access devices associated with semiconductor constructions 有权
    形成与半导体结构相关联的凹陷接入设备的方法

    公开(公告)号：US07384849B2

    公开(公告)日：2008-06-10

    申请号：US11090529

    申请日：2005-03-25

    申请人： Kunal R. Parekh ,  Suraj Mathew ,  Jigish D. Trivedi ,  John K. Zahurak ,  Sanh D. Tang

    发明人： Kunal R. Parekh ,  Suraj Mathew ,  Jigish D. Trivedi ,  John K. Zahurak ,  Sanh D. Tang

    IPC分类号： H01L21/336

    CPC分类号： H01L27/10876 ,  H01L27/10823

    摘要： The invention includes methods of forming recessed access devices. A substrate is provided to have recessed access device trenches therein. A pair of the recessed access device trenches are adjacent one another. Electrically conductive material is formed within the recessed access device trenches, and source/drain regions are formed proximate the electrically conductive material. The electrically conductive material and source/drain regions together are incorporated into a pair of adjacent recessed access devices. After the recessed access device trenches are formed within the substrate, an isolation region trench is formed between the adjacent recessed access devices and filled with electrically insulative material to form a trenched isolation region.

    摘要翻译： 本发明包括形成凹入进入装置的方法。 提供基板以在其中具有凹入的接入装置沟槽。 一对凹进的接入设备沟槽彼此相邻。 导电材料形成在凹进的存取装置沟槽内，源极/漏极区域靠近导电材料形成。 导电材料和源极/漏极区域一起被并入一对相邻的凹进入器件中。 在凹陷的访问设备沟槽形成在衬底内之后，在相邻的凹进的访问设备之间形成隔离区沟槽，并且填充有电绝缘材料以形成沟槽隔离区域。

    Capacitor structures, DRAM cell structures, and integrated circuitry, and methods of forming capacitor structures, integrated circuitry and DRAM cell structures
    128.
    发明授权
    Capacitor structures, DRAM cell structures, and integrated circuitry, and methods of forming capacitor structures, integrated circuitry and DRAM cell structures 有权
    电容器结构，DRAM单元结构和集成电路，以及形成电容器结构，集成电路和DRAM单元结构的方法

    公开(公告)号：US07151291B2

    公开(公告)日：2006-12-19

    申请号：US11074107

    申请日：2005-03-07

    申请人： Kunal R. Parekh ,  John K. Zahurak

    发明人： Kunal R. Parekh ,  John K. Zahurak

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10888 ,  H01L21/76895 ,  H01L27/10811 ,  H01L27/10855 ,  H01L28/84 ,  Y10S438/964

    摘要： The invention encompasses DRAM constructions, capacitor constructions, integrated circuitry, and methods of forming DRAM constructions, integrated circuitry and capacitor constructions. The invention encompasses a method of forming a capacitor wherein: a) a first layer is formed; b) a semiconductive material masking layer is formed over the first layer; c) an opening is etched through the masking layer and first layer to a node; d) a storage node layer is formed within the opening and in electrical connection with the masking layer; e) a capacitor storage node is formed from the masking layer and the storage node layer; and f) a capacitor dielectric layer and outer capacitor plate are formed operatively proximate the capacitor storage node.

    摘要翻译： 本发明包括DRAM结构，电容器结构，集成电路以及形成DRAM结构，集成电路和电容器结构的方法。 本发明包括形成电容器的方法，其中：a）形成第一层; b）在第一层上形成半导体材料掩蔽层; c）通过掩模层和第一层将一个开口蚀刻到一个节点上; d）存储节点层形成在所述开口内并与所述掩蔽层电连接; e）从掩蔽层和存储节点层形成电容器存储节点; 以及f）在电容器存储节点处可操作地形成电容器介电层和外部电容器板。

    Methods of forming field effect transistor gates
    129.
    发明授权
    Methods of forming field effect transistor gates 有权
    形成场效应晶体管栅极的方法

    公开(公告)号：US07081416B2

    公开(公告)日：2006-07-25

    申请号：US10406916

    申请日：2003-04-04

    申请人： John K. Zahurak ,  David K. Hwang

    发明人： John K. Zahurak ,  David K. Hwang

    IPC分类号： H01L21/302

    CPC分类号： H01L29/6659 ,  H01L21/28044 ,  H01L29/4933 ,  H01L29/6656 ,  H01L29/7833

    摘要： The invention includes methods of forming field effect transistor gates. In one implementation, a series of layers is formed proximate a semiconductive material channel region. The layers comprise a gate dielectric layer and a conductive metal-comprising layer having an ion implanted polysilicon layer received therebetween. Patterned masking material is formed over the series of layers. Using the patterned masking material as a mask, etching is conducted through the conductive metal-comprising layer and only partially into the ion implanted polysilicon layer. After such etching, the ion implanted polysilicon is annealed effective to electrically activate implanted impurity atoms received therein. Other aspects and implementations are contemplated.

    摘要翻译： 本发明包括形成场效应晶体管栅极的方法。 在一个实现中，在半导体材料沟道区域附近形成一系列层。 这些层包括栅极电介质层和在其间容纳离子注入的多晶硅层的导电金属层。 在一系列层上形成图案化掩模材料。 使用图案化掩模材料作为掩模，通过导电金属包层进行蚀刻，并且仅部分地进入离子注入的多晶硅层。 在这种蚀刻之后，离子注入的多晶硅被退火有效地电激活其中接收的注入杂质原子。 考虑了其他方面和实现。

    High pressure anneals of integrated circuit structures
    130.
    发明授权
    High pressure anneals of integrated circuit structures 失效
    集成电路结构的高压退火

    公开(公告)号：US06974773B2

    公开(公告)日：2005-12-13

    申请号：US09761355

    申请日：2001-01-16

    申请人： Randhir P. S. Thakur ,  John K. Zahurak

    发明人： Randhir P. S. Thakur ,  John K. Zahurak

    IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/00

    CPC分类号： H01L21/76856 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76882 ,  Y10S438/909

    摘要： According to one embodiment of the invention, a high pressure anneal is utilized to form titanium silicide at the bottom of a contact hole, at a pressure of at least approximately 1.1 atmospheres, from a reaction between deposited titanium and underlying silicon. When such high pressures are used, temperatures of less than approximately 700 degrees Celsius are utilized. According to another embodiment of the invention, a conductive plug fill material is deposited within a contact hole such that the plug structure is relatively free of voids. Either during deposition of the conductive plug fill material or after such deposition, the conductive plug fill material is subjected to a high pressure force-fill, at a pressure of at least approximately 1.1 atmospheres. When such high pressures are used, temperatures of less than approximately 700 degrees Celsius are utilized for the force-fill. Aluminum can be used for the conductive plug fill material when using this embodiment of the invention. In further embodiments, dielectrics deposited between conductive layers are reflowed at high pressure and low temperature. Still further, multiple metalized layers are connected by vias filled with conductive material using high pressure and low temperature.

    摘要翻译： 根据本发明的一个实施例，利用高压退火在接触孔的底部，在沉积的钛和下面的硅之间的反应压力至少约1.1个大气压下形成硅化钛。 当使用这样的高压时，使用小于约700摄氏度的温度。 根据本发明的另一个实施例，导电插塞填充材料沉积在接触孔内，使得插塞结构相对没有空隙。 在沉积导电插塞填充材料期间或在这种沉积之后，导电插塞填充材料在至少约1.1个大气压的压力下经受高压力填充。 当使用这种高压时，小于约700摄氏度的温度被用于强制填充。 当使用本发明的该实施例时，铝可用于导电塞填充材料。 在另外的实施例中，沉积在导电层之间的电介质在高压和低温下回流。 此外，多个金属化层通过使用高压和低温填充导电材料的通孔连接。