公开(公告)号：US20080258815A1

公开(公告)日：2008-10-23

申请号：US11871451

申请日：2007-10-12

Applicant: Kazuhide ABE ,  Tadahiro Sasaki ,  Kazuhiko Itaya ,  Hideyuki Funaki

Inventor： Kazuhide ABE ,  Tadahiro Sasaki ,  Kazuhiko Itaya ,  Hideyuki Funaki

IPC: H03F3/16

CPC classification number: H03F3/245 ,  H01L23/66 ,  H01L27/0207 ,  H01L2223/6644 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03F3/195 ,  H03F3/211 ,  H03F3/601 ,  H03F2200/366 ,  H03F2200/451 ,  H03F2203/21178 ,  H01L2924/00

Abstract: An object is to provide a high frequency power amplifier in which lowering of output power during operation is prevented, influence of thermal noise is suppressed, high frequency operation is stable, and long-term reliability is ensured. The high frequency power amplifier includes a plurality of transistors having gate electrodes, source regions and drain regions, the gate electrodes, source regions and drain regions being respectively connected in common, and a plurality of acoustic reflection layers being buried in portions of the semiconductor substrate, the portions being located between adjacent transistors, the acoustic reflection layers being disposed in a direction which is oblique to a length direction of the gate electrode.

Abstract translation: 本发明的目的是提供一种高频功率放大器，其中防止了操作期间输出功率的降低，热噪声的影响被抑制，高频操作稳定，并且确保了长期的可靠性。 高频功率放大器包括具有栅电极，源极区和漏极区的多个晶体管，栅电极，源极区和漏区共同分别连接，并且多个声反射层被埋在半导体衬底的一部分中 ，所述部分位于相邻的晶体管之间，声反射层沿与栅电极的长度方向倾斜的方向设置。

公开(公告)号：US20080181353A1

公开(公告)日：2008-07-31

申请号：US11858822

申请日：2007-09-20

Applicant: Masako Ogata ,  Kazuhiro Suzuki ,  Hideyuki Funaki ,  Kazuhiko Itaya

Inventor： Masako Ogata ,  Kazuhiro Suzuki ,  Hideyuki Funaki ,  Kazuhiko Itaya

IPC: G01B7/14

CPC classification number: H03K17/955 ,  G01D5/2417 ,  H03K2217/960755

Abstract: A sensor device for detecting a positional relationship between a first member and a second member, includes a first charge-holding electrode provided on a surface of the first member and holding a charge, a second charge-holding electrode provided on the surface of the first member and holding a charge differing from the charge held by the first charge-holding electrode, a first charge-induced electrode provided on a surface of the second member, the first charge-induced electrode having a charge induced therein in accordance with the charge held by the first charge-holding electrode, when the first charge-holding electrode approaches the first charge-induced electrode, a second charge-induced electrode provided on the surface of the second member, the second charge-induced electrode having a charge induced therein in accordance with the charge held by the second charge-holding electrode, when the second charge-holding electrode approaches the second charge-induced electrode.

Abstract translation: 一种用于检测第一构件和第二构件之间的位置关系的传感器装置，包括设置在第一构件的表面上并保持电荷的第一电荷保持电极，设置在第一构件和第二构件的表面上的第二电荷保持电极 并且保持与第一电荷保持电极所保持的电荷不同的电荷，设置在第二部件的表面上的第一电荷感应电极，第一电荷感应电极根据电荷保持在其中诱导电荷 通过第一电荷保持电极，当第一电荷保持电极接近第一电荷感应电极时，设置在第二元件的表面上的第二电荷感应电极，其中在其中引入电荷的第二电荷感应电极 根据第二电荷保持电极保持的电荷，当第二电荷保持电极接近第二电荷感应电极时。

公开(公告)号：US07015472B2

公开(公告)日：2006-03-21

申请号：US11063545

申请日：2005-02-24

Applicant: Sumio Ikegawa ,  Kohei Nakayama ,  Hideyuki Funaki ,  Yoshinori Iida ,  Keitaro Shigenaka

Inventor： Sumio Ikegawa ,  Kohei Nakayama ,  Hideyuki Funaki ,  Yoshinori Iida ,  Keitaro Shigenaka

IPC: H01L31/062 ,  H01L31/113 ,  H01L31/058

CPC classification number: H04N5/33 ,  G01J5/20 ,  G01J5/22 ,  G01J5/24 ,  G01J2005/202 ,  H01L27/16

Abstract: An imaging device comprises a select line, a first signal line crossing the select line, and a first pixel provided at a portion corresponding to a crossing portion of the select line and the first signal line, the first pixel comprising a first buffer layer formed on a substrate, a first bolometer film formed on the first buffer layer, made of a compound which undergoes metal-insulator transition, and generating a first temperature detection signal, a first switching element formed on the substrate, selected by a select signal from the select line, and supplying the first temperature detection signal to the first signal line, and a metal wiring connecting a top surface of the first bolometer film to the first switching element.

Abstract translation: 成像装置包括选择线，与选择线交叉的第一信号线和设置在与选择线和第一信号线的交叉部分对应的部分处的第一像素，第一像素包括形成在第一信号线上的第一缓冲层 基板，形成在第一缓冲层上的第一测辐射热计薄膜，由经历金属 - 绝缘体转变的化合物制成，并产生第一温度检测信号，形成在基板上的第一开关元件，通过来自选择的选择信号选择 并且将第一温度检测信号提供给第一信号线，以及将第一测辐射热计薄膜的顶表面连接到第一开关元件的金属布线。

公开(公告)号：US06984856B1

公开(公告)日：2006-01-10

申请号：US10392826

申请日：2003-03-21

Applicant: Sumio Ikegawa ,  Kohei Nakayama ,  Hideyuki Funaki ,  Yoshinori Iida ,  Keitaro Shigenaka

Inventor： Sumio Ikegawa ,  Kohei Nakayama ,  Hideyuki Funaki ,  Yoshinori Iida ,  Keitaro Shigenaka

IPC: H01L31/0623 ,  H01L31/113 ,  H01L31/058

CPC classification number: H04N5/33 ,  G01J5/20 ,  G01J5/22 ,  G01J5/24 ,  G01J2005/202 ,  H01L27/16

Abstract: An imaging device comprises a select line, a first signal line crossing the select line, and a first pixel provided at a portion corresponding to a crossing portion of the select line and the first signal line, the first pixel comprising a first buffer layer formed on a substrate, a first bolometer film formed on the first buffer layer, made of a compound which undergoes metal-insulator transition, and generating a first temperature detection signal, a first switching element formed on the substrate, selected by a select signal from the select line, and supplying the first temperature detection signal to the first signal line, and a metal wiring connecting a top surface of the first bolometer film to the first switching element.

公开(公告)号：US6069396A

公开(公告)日：2000-05-30

申请号：US40305

申请日：1998-03-18

Applicant: Hideyuki Funaki

Inventor： Hideyuki Funaki

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78 ,  H01L29/861 ,  H01L23/58

CPC classification number: H01L29/7824 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/7394 ,  H01L29/8611 ,  H01L29/0615 ,  H01L2924/0002

Abstract: The high breakdown voltage semiconductor device comprises an insulating film, a semi-insulating high resistance film formed on the insulating film, a first semiconductor layer of the first conductivity type formed on the high resistance film, a second semiconductor layer of the second conductivity type formed on a surface of the first semiconductor layer, a third semiconductor layer of the first conductivity type formed on the surface of the first semiconductor layer so as to be apart from the second semiconductor layer, and having an impurity concentration higher than that of the first semiconductor layer, and a resurf layer formed in a space between the second and third semiconductor layers on the surface of the first semiconductor layer, and having an impurity concentration lower than that of the second semiconductor layer.

Abstract translation: 高击穿电压半导体器件包括绝缘膜，形成在绝缘膜上的半绝缘高电阻膜，形成在高电阻膜上的第一导电类型的第一半导体层，形成第二导电类型的第二半导体层 在第一半导体层的表面上形成第一导电类型的第三半导体层，其形成在第一半导体层的表面上以与第二半导体层分离，并且具有比第一半导体层的杂质浓度更高的杂质浓度 层，以及形成在第一半导体层的表面上的第二和第三半导体层之间的空间中并且具有比第二半导体层的杂质浓度低的杂质浓度的再生层。

公开(公告)号：US5920087A

公开(公告)日：1999-07-06

申请号：US970103

申请日：1997-11-13

Applicant: Akio Nakagawa ,  Tomoko Matsudai ,  Hideyuki Funaki

Inventor： Akio Nakagawa ,  Tomoko Matsudai ,  Hideyuki Funaki

IPC: H01L21/331 ,  H01L29/06 ,  H01L29/739 ,  H01L29/74 ,  H01L27/01 ,  H01L31/111

CPC classification number: H01L29/66325 ,  H01L29/0696 ,  H01L29/7394 ,  H01L29/7398

Abstract: A sub-gate electrode is arranged to face, through a gate insulating film, a surface of a first p-type base layer which is interposed between a first n-type source layer and an n-type drift layer, and a surface of a second p-type base layer which is interposed between a second n-type source layer and the n-type drift layer and faces the first p-type base layer. A main gate electrode is arranged to face, through a gate insulating film, a surface of the second p-type base layer which is interposed between the second n-type source layer and the n-type drift layer and does not face the first p-type base layer. Three n-type MOSFETs are constructed such that one n-type channel is to be formed in the first p-type base layer and two n-type channels are to be formed in the second p-type base layer. The three channels are to be formed, so that the channel width is effectively enlarged and the current density is increased. The second p-type base layer has a length of 10 .mu.m or less in the drifting direction.

Abstract translation: 子栅电极配置成通过栅极绝缘膜与介于第一n型源极层和n型漂移层之间的第一p型基极层的表面和 第二p型基极层，其介于第二n型源极层和n型漂移层之间并且面向第一p型基极层。 主栅极布置成通过栅极绝缘膜面对介于第二n型源极层和n型漂移层之间的第二p型基极层的表面，并且不面向第一p 型基层。 构造三个n型MOSFET，使得在第一p型基极层中形成一个n型沟道，并且在第二p型基极层中形成两个n型沟道。 要形成三个通道，从而有效地扩大通道宽度，增加电流密度。 第二p型基层在漂移方向上的长度为10μm以下。

公开(公告)号：US5751022A

公开(公告)日：1998-05-12

申请号：US806153

申请日：1997-02-25

Applicant: Norio Yasuhara ,  Akio Nakagawa ,  Tomoko Matsudai ,  Hideyuki Funaki

Inventor： Norio Yasuhara ,  Akio Nakagawa ,  Tomoko Matsudai ,  Hideyuki Funaki

IPC: H01L29/74 ,  H01L29/745 ,  H01L29/749 ,  H01L31/111

CPC classification number: H01L29/749 ,  H01L29/7412 ,  H01L29/7436 ,  H01L29/7455

Abstract: A semiconductor device is disclosed having a thyristor region coupled to a semiconductor switching device and a semiconductor rectifier. During turn-off operation, holes are drained from the p-type base region of the thyristor region through the semiconductor rectifier and to the cathode of the thyristor. During turn-on, electrons are supplied to an n-type emitter region of the thyristor from the cathode electrode through the semiconductor switching device.

Abstract translation: 公开了具有耦合到半导体开关器件和半导体整流器的晶闸管区域的半导体器件。 在关断操作期间，从晶闸管区域的p型基极区域通过半导体整流器和晶闸管的阴极排出孔。 在导通期间，电子通过半导体开关器件从阴极电极提供给晶闸管的n型发射极区域。

公开(公告)号：US5731603A

公开(公告)日：1998-03-24

申请号：US701500

申请日：1996-08-22

Applicant: Akio Nakagawa ,  Tomoko Matsudai ,  Hideyuki Funaki

Inventor： Akio Nakagawa ,  Tomoko Matsudai ,  Hideyuki Funaki

IPC: H01L21/331 ,  H01L29/06 ,  H01L29/739 ,  H01L29/74 ,  H01L27/01 ,  H01L31/111

CPC classification number: H01L29/66325 ,  H01L29/0696 ,  H01L29/7394 ,  H01L29/7398

Abstract: A sub-gate electrode is arranged to face, through a gate insulating film, a surface of a first p-type base layer which is interposed between a first n-type source layer and an n-type drift layer, and a surface of a second p-type base layer which is interposed between a second n-type source layer and the n-type drift layer and faces the first p-type base layer. A main gate electrode is arranged to face, through a gate insulating film, a surface of the second p-type base layer which is interposed between the second n-type source layer and the n-type drift layer and does not face the first p-type base layer. Three n-type MOSFETs are constructed such that one n-type channel is to be formed in the first p-type base layer and two n-type channels are to be formed in the second p-type base layer. The three channels are to be formed, so that the channel width is effectively enlarged and the current density is increased. The second p-type base layer has a length of 10 .mu.m or less in the drifting direction.