公开(公告)号：US20050196947A1

公开(公告)日：2005-09-08

申请号：US11022056

申请日：2004-12-23

申请人： Hyeoung-Won Seo ,  Du-Heon Song ,  Dae-Joong Won ,  Sang-Hyun Lee

发明人： Hyeoung-Won Seo ,  Du-Heon Song ,  Dae-Joong Won ,  Sang-Hyun Lee

IPC分类号： H01L21/336 ,  H01L21/8238

CPC分类号： H01L21/823437 ,  H01L21/823412 ,  H01L21/823481 ,  H01L27/0727 ,  H01L29/66621 ,  H01L29/66659

摘要： The method of manufacturing a recess type MOS transistor improves a refresh characteristic. In the method, a channel impurity region is formed by ion implanting a first conductive impurity in an active region of a semiconductor substrate. Thereon, a second conductive impurity and the first conductive impurity are ion-implanted each alternately into the active region, to thus sequentially form first to third impurity regions having a dual diode structure on the channel impurity region, the second conductive impurity having conductivity opposite to the first conductive impurity. A trench is formed, and a gate insulation layer is formed in a gate region to produce a gate stack. The first conductive impurity is selectively ion-implanted in a source region, to thus form a fourth impurity region. A spacer is then formed in a sidewall of the gate stack, and the second conductive impurity is ion-implanted in the source/drain regions, to form a fifth impurity region.

摘要翻译： 制造凹型MOS晶体管的方法提高了刷新特性。 在该方法中，通过在半导体衬底的有源区中离子注入第一导电杂质形成沟道杂质区。 其次，将第二导电杂质和第一导电杂质各自离子注入到有源区中，从而顺序地在沟道杂质区上形成具有双二极管结构的第一至第三杂质区，第二导电杂质具有与 第一导电杂质。 形成沟槽，并且在栅极区域中形成栅极绝缘层以产生栅极堆叠。 选择性地将第一导电杂质离子注入源极区，从而形成第四杂质区。 然后在栅极堆叠的侧壁中形成间隔物，并且将第二导电杂质离子注入源极/漏极区域中，以形成第五杂质区域。

公开(公告)号：US20050194597A1

公开(公告)日：2005-09-08

申请号：US11073246

申请日：2005-03-04

申请人： Hyeoung-Won Seo ,  Du-Heon Song ,  Sang-Hyun Lee

发明人： Hyeoung-Won Seo ,  Du-Heon Song ,  Sang-Hyun Lee

IPC分类号： H01L27/108 ,  H01L21/00 ,  H01L29/12

CPC分类号： H01L27/10891 ,  H01L27/10823 ,  H01L27/1087

摘要： According to some embodiments of the invention, transistors of a semiconductor device have a channel region in a channel-portion hole. Methods include forming embodiments of the transistor having a channel-portion hole disposed in a semiconductor substrate. A channel-portion trench pad and a channel-portion layer are sequentially formed at a lower portion of the channel-portion hole. A word line insulating layer pattern and a word line pattern are sequentially stacked on the channel-portion layer and fill the channel-portion hole, disposed on the semiconductor substrate. The channel-portion layer is formed to contact the semiconductor substrate through a portion of sidewall of the channel-portion hole, and forms a channel region under the word line pattern. Punchthrough is prevented between electrode impurity regions corresponding to source and drain regions.

摘要翻译： 根据本发明的一些实施例，半导体器件的晶体管在沟道部分孔中具有沟道区。 方法包括形成具有设置在半导体衬底中的沟道部分孔的晶体管的实施例。 通道部分沟槽焊盘和沟道部分层依次形成在沟道部分孔的下部。 字线绝缘层图案和字线图案依次层叠在沟道部分层上并填充设置在半导体衬底上的沟道部分孔。 沟道部分层形成为通过沟道部分孔的侧壁的一部分与半导体衬底接触，并在字线图案下形成沟道区。 防止对应于源区和漏区的电极杂质区之间的穿透。

公开(公告)号：US20050184643A1

公开(公告)日：2005-08-25

申请号：US11066854

申请日：2005-02-24

申请人： Sung-Hee Cho ,  Jong-Hwan Park ,  Sang-Hyun Lee

发明人： Sung-Hee Cho ,  Jong-Hwan Park ,  Sang-Hyun Lee

IPC分类号： H01J29/04 ,  H01J1/304 ,  H01J1/62 ,  H01J9/02 ,  H01J31/12

CPC分类号： H01J1/304 ,  B82Y10/00 ,  H01J9/025 ,  H01J31/127 ,  H01J2201/30446

摘要： The present invention relates to a method for forming an electron emission source for an electron emission device and an electron emission device produced by the method. The method for forming an electron emission source comprises: depositing at least one kind of charged particles selected from the group consisting of carbon-based materials, metal particles, inorganic particles, and organic materials to a substrate charged by the opposite charge. The method provides an electron emission source for an electron emission device upon which carbon nanotubes are selectively deposited in a desired pattern without leaving surplus organic carbon. The resulting electron emission devices exhibit excellent life and electron emission characteristics. The method does not require additional surface treatment.

摘要翻译： 本发明涉及用于形成电子发射器件的电子发射源的方法和通过该方法制造的电子发射器件。 形成电子发射源的方法包括：将从碳基材料，金属颗粒，无机颗粒和有机材料中选出的至少一种带电粒子沉积到由相反电荷充电的衬底上。 该方法提供了电子发射装置的电子发射源，在该电子发射装置上，以期望的图案选择性地沉积碳纳米管，而不留下剩余的有机碳。 所得到的电子发射器件具有优异的寿命和电子发射特性。 该方法不需要额外的表面处理。

公开(公告)号：US20050133836A1

公开(公告)日：2005-06-23

申请号：US11021349

申请日：2004-12-23

申请人： Hyeoung-Won Seo ,  Dong-Hyun Kim ,  Du-Heon Song ,  Sang-Hyun Lee

发明人： Hyeoung-Won Seo ,  Dong-Hyun Kim ,  Du-Heon Song ,  Sang-Hyun Lee

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/7835 ,  H01L29/1045 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66659

摘要： a A MOS (metal oxide semiconductor) transistor with a trench-type gate is fabricated with a channel stopping region for forming an asymmetric channel region for reducing short channel effects. For example in fabricating an N-channel MOS transistor, a gate structure is formed within a trench that is within a P-well. A channel stopping region with a P-type dopant is formed to a first side of the trench to completely contain an N-type source junction therein. An N-type drain junction is formed within a LDD region to a second side of the trench, thus forming the asymmetric channel region.

摘要翻译： 制造具有沟槽型栅极的MOS（金属氧化物半导体）晶体管，其具有用于形成用于减小短沟道效应的不对称沟道区的沟道停止区域。 例如在制造N沟道MOS晶体管时，栅极结构形成在P阱内的沟槽内。 在沟槽的第一侧形成具有P型掺杂剂的沟道停止区，以在其中完全包含N型源极结。 在LDD区内形成N型漏极结至沟槽的第二侧，从而形成非对称沟道区。

公开(公告)号：US20050032480A1

公开(公告)日：2005-02-10

申请号：US10606822

申请日：2003-06-26

申请人： Sang-Hyun Lee ,  Kwang-Soon Kim ,  Yun-Hee Kim ,  Kyung-Hi Chang

发明人： Sang-Hyun Lee ,  Kwang-Soon Kim ,  Yun-Hee Kim ,  Kyung-Hi Chang

IPC分类号： H04B1/40 ,  H04L27/00

CPC分类号： H04B1/0007 ,  H04B1/0003 ,  H04B1/406 ,  H04L27/0008

摘要： Disclosed is a receiver digital filter for a digital IF signal processor suitable for the specification of each communication standard in a communication system that supports at least one communication standard. The filter for each standard is constructed as one block, and includes a block for externally implementing the constructed block. The coefficient of the digital filter constructed in one block is implemented with an external input or an internal filter coefficient calculator by a basic filter building block. In this manner, the common resources required in the digital filter used in each communication standard are shared, and only the additionally required resources are selectively implemented. Since the shared resources are calculated by dynamic programming, a considerably smaller number of additional resources are required.

摘要翻译： 公开了一种用于数字IF信号处理器的接收机数字滤波器，其适用于支持至少一个通信标准的通信系统中的每个通信标准的规范。 每个标准的滤波器被构造为一个块，并且包括用于外部实现构造块的块。 在一个块中构造的数字滤波器的系数由基本滤波器构建块的外部输入或内部滤波器系数计算器实现。 以这种方式，在每个通信标准中使用的数字滤波器中所需的共同资源被共享，并且仅选择性地实现附加所需的资源。 由于共享资源是通过动态规划计算的，所以需要相当少的额外资源。

公开(公告)号：US5883846A

公开(公告)日：1999-03-16

申请号：US901627

申请日：1997-07-28

申请人： Sang-Hyun Lee

发明人： Sang-Hyun Lee

IPC分类号： G11C11/419 ,  G11C7/06 ,  G11C11/409 ,  G11C7/02

CPC分类号： G11C7/065

摘要： A latch type sense amplifier having negative feedback means for use in a memory device includes a first switching unit which is turned on/off by an enable signal and initializes a system operation at a turn-on operation; a second switching unit which is turned on/off according to the voltage state of the data on two data lines at the turn-on operation of the first switching unit and performs a system initial operation; a third switching unit which is turned on by a precharge signal and initializes two output signals; a latch unit for latching the data input via the second switching unit according to the operation of the third switching unit and outputting the latched data to two data output units; and a feedback switching unit which is connected to the data output units of the latch unit and the data lines, is turned on/off according to the voltage state of the other data output unit and pulls-up the voltage difference of the bit line connected to corresponding data line by the voltage on corresponding data output terminal at an on operation.

摘要翻译： 具有用于存储器件的负反馈装置的锁存型读出放大器包括：第一开关单元，其通过使能信号导通/截止，并在导通操作下初始化系统操作; 第二开关单元，其在第一开关单元的导通动作下，根据两条数据线上的数据的电压状态接通/断开，并执行系统初始操作; 第三开关单元，其通过预充电信号导通并初始化两个输出信号; 锁存单元，用于根据第三开关单元的操作锁存经由第二开关单元输入的数据，并将锁存的数据输出到两个数据输出单元; 并且连接到锁存单元和数据线的数据输出单元的反馈切换单元根据其他数据输出单元的电压状态被接通/断开，并且上拉连接的位线的电压差 通过相应的数据输出端子上的电压在相应的数据线上。