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141 条记录 (耗时 0.032 秒)

    Asymmetric MOS transistor with trench-type gate
    4.
    发明申请
    Asymmetric MOS transistor with trench-type gate 有权
    具有沟槽型栅极的非对称MOS晶体管

    公开(公告)号：US20050133836A1

    公开(公告)日：2005-06-23

    申请号：US11021349

    申请日：2004-12-23

    申请人： Hyeoung-Won Seo ,  Dong-Hyun Kim ,  Du-Heon Song ,  Sang-Hyun Lee

    发明人： Hyeoung-Won Seo ,  Dong-Hyun Kim ,  Du-Heon Song ,  Sang-Hyun Lee

    IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/76 ,  H01L29/78

    CPC分类号： H01L29/7835 ,  H01L29/1045 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66659

    摘要： a A MOS (metal oxide semiconductor) transistor with a trench-type gate is fabricated with a channel stopping region for forming an asymmetric channel region for reducing short channel effects. For example in fabricating an N-channel MOS transistor, a gate structure is formed within a trench that is within a P-well. A channel stopping region with a P-type dopant is formed to a first side of the trench to completely contain an N-type source junction therein. An N-type drain junction is formed within a LDD region to a second side of the trench, thus forming the asymmetric channel region.

    摘要翻译： 制造具有沟槽型栅极的MOS（金属氧化物半导体）晶体管，其具有用于形成用于减小短沟道效应的不对称沟道区的沟道停止区域。 例如在制造N沟道MOS晶体管时，栅极结构形成在P阱内的沟槽内。 在沟槽的第一侧形成具有P型掺杂剂的沟道停止区，以在其中完全包含N型源极结。 在LDD区内形成N型漏极结至沟槽的第二侧，从而形成非对称沟道区。

    Method of forming asymmetric MOS transistor with a channel stopping region and a trench-type gate
    5.
    发明授权
    Method of forming asymmetric MOS transistor with a channel stopping region and a trench-type gate 有权
    形成具有通道停止区域的非对称MOS晶体管和沟槽型栅极的方法

    公开(公告)号：US07378320B2

    公开(公告)日：2008-05-27

    申请号：US11021349

    申请日：2004-12-23

    申请人： Hyeoung-Won Seo ,  Dong-Hyun Kim ,  Du-Heon Song ,  Sang-Hyun Lee

    发明人： Hyeoung-Won Seo ,  Dong-Hyun Kim ,  Du-Heon Song ,  Sang-Hyun Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7835 ,  H01L29/1045 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66659

    摘要： A MOS (metal oxide semiconductor) transistor with a trench-type gate is fabricated with a channel stopping region for forming an asymmetric channel region for reducing short channel effects. For example in fabricating an N-channel MOS transistor, a gate structure is formed within a trench that is within a P-well. A channel stopping region with a P-type dopant is formed to a first side of the trench to completely contain an N-type source junction therein. An N-type drain junction is formed within a LDD region to a second side of the trench, thus forming the asymmetric channel region.

    摘要翻译： 制造具有沟槽型栅极的MOS（金属氧化物半导体）晶体管，其具有沟道停止区域，用于形成用于减小短沟道效应的不对称沟道区域。 例如在制造N沟道MOS晶体管时，栅极结构形成在P阱内的沟槽内。 在沟槽的第一侧形成具有P型掺杂剂的沟道停止区，以在其中完全包含N型源极结。 在LDD区内形成N型漏极结至沟槽的第二侧，从而形成非对称沟道区。

    Recess gate-type semiconductor device and method of manufacturing the same
    6.
    发明授权
    Recess gate-type semiconductor device and method of manufacturing the same 失效
    嵌入式门式半导体器件及其制造方法

    公开(公告)号：US07323746B2

    公开(公告)日：2008-01-29

    申请号：US11228041

    申请日：2005-09-14

    申请人： Won-Mo Park ,  Jae-Choel Paik ,  Du-Heon Song ,  Dong-Hyun Kim ,  Chang-Sub Lee

    发明人： Won-Mo Park ,  Jae-Choel Paik ,  Du-Heon Song ,  Dong-Hyun Kim ,  Chang-Sub Lee

    IPC分类号： H01L27/108 ,  H01L29/94

    CPC分类号： H01L29/0692 ,  H01L29/4236

    摘要： A recess gate-type semiconductor device includes a gate electrode having a recessed portion at least partially covering a recess trench in an active region, and source/drain regions disposed in the active region that are separated by the gate electrode. The recess trench is separated from sidewalls of a device isolation region in a first direction and contacts sidewalls of the device isolation region in a second direction. The width of the recess trench of the active region in the second direction may be greater than the width of the source/drain regions in the second direction, and the recessed portion of the gate electrode may have tabs protruding in the first direction at its corners. Therefore, the semiconductor device has excellent junction leakage current and excellent refresh characteristics.

    摘要翻译： 凹槽型半导体器件包括具有至少部分地覆盖有源区中的凹槽的凹部的栅电极和设置在有源区中的由栅电极分离的源/漏区。 所述凹槽在第一方向上与器件隔离区的侧壁分离，并沿着第二方向接触器件隔离区的侧壁。 有源区在第二方向上的凹槽的宽度可以大于第二方向上的源极/漏极区的宽度，并且栅电极的凹陷部分可以具有在其角部沿第一方向突出的突出部 。 因此，半导体器件具有优异的结漏电流和优异的刷新特性。

    Method of manufacturing a semiconductor device
    7.
    发明授权
    Method of manufacturing a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US07205208B2

    公开(公告)日：2007-04-17

    申请号：US11147312

    申请日：2005-06-08

    申请人： Dong-Hyun Kim ,  Du-Heon Song

    发明人： Dong-Hyun Kim ,  Du-Heon Song

    IPC分类号： H01L21/76 ,  H01L21/4763 ,  H01L21/3205 ,  H01L21/336

    CPC分类号： H01L29/7834 ,  H01L21/76229 ,  H01L21/763 ,  H01L27/10876 ,  H01L29/66621

    摘要： In a method of manufacturing a semiconductor device, a first trench is formed in a first region of a substrate and a second trench is formed in a second region of the substrate different from the first region. A depth of the first trench is less than that of the second trench. An insulation layer is formed in the second trench, so that semiconductor structures in the first trench are electrically isolated, and a conductive layer fills the first trench and extends above the first trench.

    摘要翻译： 在制造半导体器件的方法中，第一沟槽形成在衬底的第一区域中，并且第二沟槽形成在不同于第一区域的衬底的第二区域中。 第一沟槽的深度小于第二沟槽的深度。 在第二沟槽中形成绝缘层，使得第一沟槽中的半导体结构被电隔离，并且导电层填充第一沟槽并在第一沟槽之上延伸。

    Method of manufacturing a semiconductor device
    8.
    发明申请
    Method of manufacturing a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US20050272199A1

    公开(公告)日：2005-12-08

    申请号：US11147312

    申请日：2005-06-08

    申请人： Dong-Hyun Kim ,  Du-Heon Song

    发明人： Dong-Hyun Kim ,  Du-Heon Song

    IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L21/763 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/8244 ,  H01L29/78

    CPC分类号： H01L29/7834 ,  H01L21/76229 ,  H01L21/763 ,  H01L27/10876 ,  H01L29/66621

    摘要： In a method of manufacturing a semiconductor device, a first trench is formed in a first region of a substrate and a second trench is formed in a second region of the substrate different from the first region. A depth of the first trench is less than that of the second trench. An insulation layer is formed in the second trench, so that semiconductor structures in the first trench are electrically isolated, and a conductive layer fills the first trench and extends above the first trench.

    摘要翻译： 在制造半导体器件的方法中，第一沟槽形成在衬底的第一区域中，并且第二沟槽形成在不同于第一区域的衬底的第二区域中。 第一沟槽的深度小于第二沟槽的深度。 在第二沟槽中形成绝缘层，使得第一沟槽中的半导体结构被电隔离，并且导电层填充第一沟槽并在第一沟槽之上延伸。

    Recess gate-type semiconductor device and method of manufacturing the same
    9.
    发明申请
    Recess gate-type semiconductor device and method of manufacturing the same 失效
    嵌入式门式半导体器件及其制造方法

    公开(公告)号：US20060060936A1

    公开(公告)日：2006-03-23

    申请号：US11228041

    申请日：2005-09-14

    申请人： Won-Mo Park ,  Jae-Choel Paik ,  Du-Heon Song ,  Dong-Hyun Kim ,  Chang-Sub Lee

    发明人： Won-Mo Park ,  Jae-Choel Paik ,  Du-Heon Song ,  Dong-Hyun Kim ,  Chang-Sub Lee

    IPC分类号： H01L29/00

    CPC分类号： H01L29/0692 ,  H01L29/4236

    摘要： A recess gate-type semiconductor device includes a gate electrode having a recessed portion at least partially covering a recess trench in an active region, and source/drain regions disposed in the active region that are separated by the gate electrode. The recess trench is separated from sidewalls of a device isolation region in a first direction and contacts sidewalls of the device isolation region in a second direction. The width of the recess trench of the active region in the second direction may be greater than the width of the source/drain regions in the second direction, and the recessed portion of the gate electrode may have tabs protruding in the first direction at its corners. Therefore, the semiconductor device has excellent junction leakage current and excellent refresh characteristics.

    摘要翻译： 凹槽型半导体器件包括具有至少部分地覆盖有源区中的凹槽的凹部的栅电极和设置在有源区中的由栅电极分离的源/漏区。 所述凹槽在第一方向上与器件隔离区的侧壁分离，并沿着第二方向接触器件隔离区的侧壁。 有源区在第二方向上的凹槽的宽度可以大于第二方向上的源极/漏极区的宽度，并且栅电极的凹陷部分可以具有在其角部沿第一方向突出的突出部 。 因此，半导体器件具有优异的结漏电流和优异的刷新特性。