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    Method of forming asymmetric MOS transistor with a channel stopping region and a trench-type gate
    3.
    发明授权
    Method of forming asymmetric MOS transistor with a channel stopping region and a trench-type gate 有权
    形成具有通道停止区域的非对称MOS晶体管和沟槽型栅极的方法

    公开(公告)号：US07378320B2

    公开(公告)日：2008-05-27

    申请号：US11021349

    申请日：2004-12-23

    申请人： Hyeoung-Won Seo ,  Dong-Hyun Kim ,  Du-Heon Song ,  Sang-Hyun Lee

    发明人： Hyeoung-Won Seo ,  Dong-Hyun Kim ,  Du-Heon Song ,  Sang-Hyun Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7835 ,  H01L29/1045 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66659

    摘要： A MOS (metal oxide semiconductor) transistor with a trench-type gate is fabricated with a channel stopping region for forming an asymmetric channel region for reducing short channel effects. For example in fabricating an N-channel MOS transistor, a gate structure is formed within a trench that is within a P-well. A channel stopping region with a P-type dopant is formed to a first side of the trench to completely contain an N-type source junction therein. An N-type drain junction is formed within a LDD region to a second side of the trench, thus forming the asymmetric channel region.

    摘要翻译： 制造具有沟槽型栅极的MOS（金属氧化物半导体）晶体管，其具有沟道停止区域，用于形成用于减小短沟道效应的不对称沟道区域。 例如在制造N沟道MOS晶体管时，栅极结构形成在P阱内的沟槽内。 在沟槽的第一侧形成具有P型掺杂剂的沟道停止区，以在其中完全包含N型源极结。 在LDD区内形成N型漏极结至沟槽的第二侧，从而形成非对称沟道区。

    Asymmetric MOS transistor with trench-type gate
    5.
    发明申请
    Asymmetric MOS transistor with trench-type gate 有权
    具有沟槽型栅极的非对称MOS晶体管

    公开(公告)号：US20050133836A1

    公开(公告)日：2005-06-23

    申请号：US11021349

    申请日：2004-12-23

    申请人： Hyeoung-Won Seo ,  Dong-Hyun Kim ,  Du-Heon Song ,  Sang-Hyun Lee

    发明人： Hyeoung-Won Seo ,  Dong-Hyun Kim ,  Du-Heon Song ,  Sang-Hyun Lee

    IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/76 ,  H01L29/78

    CPC分类号： H01L29/7835 ,  H01L29/1045 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66659

    摘要： a A MOS (metal oxide semiconductor) transistor with a trench-type gate is fabricated with a channel stopping region for forming an asymmetric channel region for reducing short channel effects. For example in fabricating an N-channel MOS transistor, a gate structure is formed within a trench that is within a P-well. A channel stopping region with a P-type dopant is formed to a first side of the trench to completely contain an N-type source junction therein. An N-type drain junction is formed within a LDD region to a second side of the trench, thus forming the asymmetric channel region.

    摘要翻译： 制造具有沟槽型栅极的MOS（金属氧化物半导体）晶体管，其具有用于形成用于减小短沟道效应的不对称沟道区的沟道停止区域。 例如在制造N沟道MOS晶体管时，栅极结构形成在P阱内的沟槽内。 在沟槽的第一侧形成具有P型掺杂剂的沟道停止区，以在其中完全包含N型源极结。 在LDD区内形成N型漏极结至沟槽的第二侧，从而形成非对称沟道区。

    Transistors of semiconductor device having channel region in a channel-portion hole and methods of forming the same
    6.
    发明授权
    Transistors of semiconductor device having channel region in a channel-portion hole and methods of forming the same 有权
    在通道部分孔中具有沟道区的半导体器件的晶体管及其形成方法

    公开(公告)号：US07696570B2

    公开(公告)日：2010-04-13

    申请号：US12350708

    申请日：2009-01-08

    申请人： Hyeoung-Won Seo ,  Du-Heon Song ,  Sang-Hyun Lee

    发明人： Hyeoung-Won Seo ,  Du-Heon Song ,  Sang-Hyun Lee

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L27/10891 ,  H01L27/10823 ,  H01L27/1087

    摘要： According to some embodiments of the invention, transistors of a semiconductor device have a channel region in a channel-portion hole. Methods include forming embodiments of the transistor having a channel-portion hole disposed in a semiconductor substrate. A channel-portion trench pad and a channel-portion layer are sequentially formed at a lower portion of the channel-portion hole. A word line insulating layer pattern and a word line pattern are sequentially stacked on the channel-portion layer and fill the channel-portion hole, disposed on the semiconductor substrate. The channel-portion layer is formed to contact the semiconductor substrate through a portion of sidewall of the channel-portion hole, and forms a channel region under the word line pattern. Punchthrough is prevented between electrode impurity regions corresponding to source and drain regions.

    摘要翻译： 根据本发明的一些实施例，半导体器件的晶体管在沟道部分孔中具有沟道区。 方法包括形成具有设置在半导体衬底中的沟道部分孔的晶体管的实施例。 通道部分沟槽焊盘和沟道部分层依次形成在沟道部分孔的下部。 字线绝缘层图案和字线图案依次层叠在沟道部分层上并填充设置在半导体衬底上的沟道部分孔。 沟道部分层形成为通过沟道部分孔的侧壁的一部分与半导体衬底接触，并在字线图案下形成沟道区。 防止对应于源区和漏区的电极杂质区之间的穿透。

    Transistors of semiconductor device having channel region in a channel-portion hole and methods of forming the same
    7.
    发明授权
    Transistors of semiconductor device having channel region in a channel-portion hole and methods of forming the same 有权
    在通道部孔中具有沟道区的半导体器件的晶体管及其形成方法

    公开(公告)号：US07491603B2

    公开(公告)日：2009-02-17

    申请号：US11073246

    申请日：2005-03-04

    申请人： Hyeoung-Won Seo ,  Du-Heon Song ,  Sang-Hyun Lee

    发明人： Hyeoung-Won Seo ,  Du-Heon Song ,  Sang-Hyun Lee

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10891 ,  H01L27/10823 ,  H01L27/1087

    摘要： According to some embodiments of the invention, transistors of a semiconductor device have a channel region in a channel-portion hole. Methods include forming embodiments of the transistor having a channel-portion hole disposed in a semiconductor substrate. A channel-portion trench pad and a channel-portion layer are sequentially formed at a lower portion of the channel-portion hole. A word line insulating layer pattern and a word line pattern are sequentially stacked on the channel-portion layer and fill the channel-portion hole, disposed on the semiconductor substrate. The channel-portion layer is formed to contact the semiconductor substrate through a portion of sidewall of the channel-portion hole, and forms a channel region under the word line pattern. Punchthrough is prevented between electrode impurity regions corresponding to source and drain regions.

    摘要翻译： 根据本发明的一些实施例，半导体器件的晶体管在沟道部分孔中具有沟道区。 方法包括形成具有设置在半导体衬底中的沟道部分孔的晶体管的实施例。 通道部分沟槽焊盘和沟道部分层依次形成在沟道部分孔的下部。 字线绝缘层图案和字线图案依次层叠在沟道部分层上并填充设置在半导体衬底上的沟道部分孔。 沟道部分层形成为通过沟道部分孔的侧壁的一部分与半导体衬底接触，并在字线图案下形成沟道区。 防止对应于源区和漏区的电极杂质区之间的穿透。

    Method of manufacturing recess type MOS transistor having a dual diode impurity layer structure
    8.
    发明授权
    Method of manufacturing recess type MOS transistor having a dual diode impurity layer structure 有权
    制造具有双二极管杂质层结构的凹型MOS晶体管的方法

    公开(公告)号：US07300845B2

    公开(公告)日：2007-11-27

    申请号：US11022056

    申请日：2004-12-23

    申请人： Hyeoung-Won Seo ,  Du-Heon Song ,  Dae-Joong Won ,  Sang-Hyun Lee

    发明人： Hyeoung-Won Seo ,  Du-Heon Song ,  Dae-Joong Won ,  Sang-Hyun Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823437 ,  H01L21/823412 ,  H01L21/823481 ,  H01L27/0727 ,  H01L29/66621 ,  H01L29/66659

    摘要： The method of manufacturing a recess type MOS transistor improves a refresh characteristic. In the method, a channel impurity region is formed by ion implanting a first conductive impurity in an active region of a semiconductor substrate. Thereon, a second conductive impurity and the first conductive impurity are ion-implanted each alternately into the active region, to thus sequentially form first to third impurity regions having a dual diode structure on the channel impurity region, the second conductive impurity having conductivity opposite to the first conductive impurity. A trench is formed, and a gate insulation layer is formed in a gate region to produce a gate stack. The first conductive impurity is selectively ion-implanted in a source region, to thus form a fourth impurity region. A spacer is then formed in a sidewall of the gate stack, and the second conductive impurity is ion-implanted in the source/drain regions, to form a fifth impurity region.

    摘要翻译： 制造凹型MOS晶体管的方法提高了刷新特性。 在该方法中，通过在半导体衬底的有源区中离子注入第一导电杂质形成沟道杂质区。 其次，将第二导电杂质和第一导电杂质各自离子注入到有源区中，从而顺序地在沟道杂质区上形成具有双二极管结构的第一至第三杂质区，第二导电杂质具有与 第一导电杂质。 形成沟槽，并且在栅极区域中形成栅极绝缘层以产生栅极堆叠。 选择性地将第一导电杂质离子注入源极区，从而形成第四杂质区。 然后在栅极堆叠的侧壁中形成间隔物，并且将第二导电杂质离子注入源极/漏极区域中，以形成第五杂质区域。

    Recess type MOS transistor and method of manufacturing same
    9.
    发明申请
    Recess type MOS transistor and method of manufacturing same 有权
    凹陷型MOS晶体管及其制造方法

    公开(公告)号：US20050196947A1

    公开(公告)日：2005-09-08

    申请号：US11022056

    申请日：2004-12-23

    申请人： Hyeoung-Won Seo ,  Du-Heon Song ,  Dae-Joong Won ,  Sang-Hyun Lee

    发明人： Hyeoung-Won Seo ,  Du-Heon Song ,  Dae-Joong Won ,  Sang-Hyun Lee

    IPC分类号： H01L21/336 ,  H01L21/8238

    CPC分类号： H01L21/823437 ,  H01L21/823412 ,  H01L21/823481 ,  H01L27/0727 ,  H01L29/66621 ,  H01L29/66659

    摘要： The method of manufacturing a recess type MOS transistor improves a refresh characteristic. In the method, a channel impurity region is formed by ion implanting a first conductive impurity in an active region of a semiconductor substrate. Thereon, a second conductive impurity and the first conductive impurity are ion-implanted each alternately into the active region, to thus sequentially form first to third impurity regions having a dual diode structure on the channel impurity region, the second conductive impurity having conductivity opposite to the first conductive impurity. A trench is formed, and a gate insulation layer is formed in a gate region to produce a gate stack. The first conductive impurity is selectively ion-implanted in a source region, to thus form a fourth impurity region. A spacer is then formed in a sidewall of the gate stack, and the second conductive impurity is ion-implanted in the source/drain regions, to form a fifth impurity region.

    摘要翻译： 制造凹型MOS晶体管的方法提高了刷新特性。 在该方法中，通过在半导体衬底的有源区中离子注入第一导电杂质形成沟道杂质区。 其次，将第二导电杂质和第一导电杂质各自离子注入到有源区中，从而顺序地在沟道杂质区上形成具有双二极管结构的第一至第三杂质区，第二导电杂质具有与 第一导电杂质。 形成沟槽，并且在栅极区域中形成栅极绝缘层以产生栅极堆叠。 选择性地将第一导电杂质离子注入源极区，从而形成第四杂质区。 然后在栅极堆叠的侧壁中形成间隔物，并且将第二导电杂质离子注入源极/漏极区域中，以形成第五杂质区域。

    Transistors of semiconductor device having channel region in a channel-portion hole and methods of forming the same
    10.
    发明申请
    Transistors of semiconductor device having channel region in a channel-portion hole and methods of forming the same 有权
    在通道部分孔中具有沟道区的半导体器件的晶体管及其形成方法

    公开(公告)号：US20050194597A1

    公开(公告)日：2005-09-08

    申请号：US11073246

    申请日：2005-03-04

    申请人： Hyeoung-Won Seo ,  Du-Heon Song ,  Sang-Hyun Lee

    发明人： Hyeoung-Won Seo ,  Du-Heon Song ,  Sang-Hyun Lee

    IPC分类号： H01L27/108 ,  H01L21/00 ,  H01L29/12

    CPC分类号： H01L27/10891 ,  H01L27/10823 ,  H01L27/1087

    摘要： According to some embodiments of the invention, transistors of a semiconductor device have a channel region in a channel-portion hole. Methods include forming embodiments of the transistor having a channel-portion hole disposed in a semiconductor substrate. A channel-portion trench pad and a channel-portion layer are sequentially formed at a lower portion of the channel-portion hole. A word line insulating layer pattern and a word line pattern are sequentially stacked on the channel-portion layer and fill the channel-portion hole, disposed on the semiconductor substrate. The channel-portion layer is formed to contact the semiconductor substrate through a portion of sidewall of the channel-portion hole, and forms a channel region under the word line pattern. Punchthrough is prevented between electrode impurity regions corresponding to source and drain regions.

    摘要翻译： 根据本发明的一些实施例，半导体器件的晶体管在沟道部分孔中具有沟道区。 方法包括形成具有设置在半导体衬底中的沟道部分孔的晶体管的实施例。 通道部分沟槽焊盘和沟道部分层依次形成在沟道部分孔的下部。 字线绝缘层图案和字线图案依次层叠在沟道部分层上并填充设置在半导体衬底上的沟道部分孔。 沟道部分层形成为通过沟道部分孔的侧壁的一部分与半导体衬底接触，并在字线图案下形成沟道区。 防止对应于源区和漏区的电极杂质区之间的穿透。