公开(公告)号：US20190326405A1

公开(公告)日：2019-10-24

申请号：US16457728

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Mauro J. Kobrinsky ,  Kimin Jun ,  Il-Seok Son ,  Paul B. Fischer

IPC: H01L29/417 ,  H01L27/12 ,  H01L21/84 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165

Abstract: Methods and structures formed thereby are described, of forming self-aligned contact structures for microelectronic devices. An embodiment includes forming a trench in a source/drain region of a transistor device disposed in a device layer, wherein the device layer is on a substrate, forming a fill material in the trench, forming a source/drain material on the fill material, forming a first source/drain contact on a first side of the source/drain material, and then forming a second source drain contact on a second side of the source/drain material.

公开(公告)号：US10068874B2

公开(公告)日：2018-09-04

申请号：US15122630

申请日：2014-06-16

Applicant: Intel Corporation

Inventor： Donald W. Nelson ,  M Clair Webb ,  Patrick Morrow ,  Kimin Jun

IPC: H01L23/34 ,  H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00

Abstract: A method including forming a first substrate including an integrated circuit device layer disposed between a plurality of first interconnects and a plurality of second interconnects; coupling a second substrate including a memory device layer to the first substrate so that the memory device layer is juxtaposed to one of the plurality of first interconnects and the plurality of second interconnects; and removing a portion of the first substrate. An apparatus including a device layer including a plurality of circuit devices disposed between a plurality of first interconnects and a plurality of second interconnects on a substrate; a memory device layer including a plurality of memory devices juxtaposed and coupled to one of the plurality of first interconnects and the plurality of second interconnects; and contacts points coupled to one of ones of the first plurality of interconnects and ones of the second plurality of interconnects.

公开(公告)号：US09685436B2

公开(公告)日：2017-06-20

申请号：US14778512

申请日：2013-06-25

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Kimin Jun ,  M. Clair Webb ,  Donald W. Nelson

IPC: H01L27/088 ,  H01L21/84 ,  H01L27/06 ,  H01L27/11 ,  H01L21/8234 ,  H01L27/12 ,  H01L21/768 ,  H01L21/822 ,  H01L23/538 ,  H01L29/78

CPC classification number: H01L27/0688 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/8221 ,  H01L21/823431 ,  H01L21/845 ,  H01L23/5386 ,  H01L27/0886 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1211 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Monolithic 3D ICs employing one or more local inter-level interconnect integrated intimately with at least one structure of at least one transistor on at least one transistor level within the 3D IC. In certain embodiments the local inter-level interconnect intersects a gate electrode or a source/drain region of at least one transistor and extends through at least one inter-level dielectric layer disposed between a first and second transistor level in the 3D IC. Local inter-level interconnects may advantageously make a direct vertical connection between transistors in different levels of the 3D IC without being routed laterally around the footprint (i.e., lateral, or planar, area) of either the overlying or underlying transistor level that is interconnected.

公开(公告)号：US09590051B2

公开(公告)日：2017-03-07

申请号：US15026614

申请日：2013-12-18

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Patrick Morrow

IPC: H01L27/02 ,  H01L29/267 ,  H01L29/66 ,  H01L29/775 ,  H01L29/06 ,  H01L29/08 ,  H01L29/41 ,  H01L27/092 ,  H01L29/36 ,  H01L29/417

CPC classification number: H01L29/267 ,  H01L21/823807 ,  H01L21/823885 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/36 ,  H01L29/413 ,  H01L29/4175 ,  H01L29/66439 ,  H01L29/775

Abstract: An embodiment includes an apparatus comprising: an N layer comprising an NMOS device having a N channel, source, and drain that are all intersected by a first horizontal axis that is parallel to a substrate; a P layer comprising a PMOS device having a P channel, source, and drain that are all intersected by a second horizontal axis that is parallel to the substrate; a first gate, corresponding to the N channel, which intersects the second horizontal axis; and a second gate, corresponding to the P channel, which intersects the first horizontal axis. Other embodiments are described herein.

Abstract translation: 实施例包括一种装置，包括：N层，包括具有N沟道，源极和漏极的NMOS器件，所述N沟道，源极和漏极都与平行于衬底的第一水平轴相交; P层，包括具有P沟道，源极和漏极的PMOS器件，所述PMOS器件都与平行于衬底的第二水平轴相交; 对应于与第二水平轴相交的N通道的第一门; 以及与P沟道相对应的与第一水平轴相交的第二门。 本文描述了其它实施例。