公开(公告)号：US20200075775A1

公开(公告)日：2020-03-05

申请号：US16559783

申请日：2019-09-04

Applicant: International Business Machines Corporation

Inventor： Wenyu Xu ,  Chen Zhang ,  Kangguo Cheng ,  Xin Miao

IPC: H01L29/786 ,  H01L29/66

Abstract: A method for manufacturing a semiconductor device includes forming a fin on a semiconductor substrate. In the method, a bottom source/drain region is formed between the fin and the semiconductor substrate, and a top source/drain region is formed on the fin. The method further includes forming a cap layer covering part of a top surface of the top source/drain region. A portion of the top source/drain region and an underlying portion of the fin not covered by the cap layer are removed. The removal exposes a portion of the bottom source/drain region. A dielectric spacer is formed on a side of the fin adjacent the exposed portion of the bottom source/drain region, and extends onto a side of the top source/drain region. A bottom source/drain contact is formed on the exposed portion of the bottom source/drain region and on the dielectric spacer.

公开(公告)号：US10566445B2

公开(公告)日：2020-02-18

申请号：US15944322

申请日：2018-04-03

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Nicolas J. Loubet ,  Xin Miao ,  Wenyu Xu ,  Chen Zhang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: Embodiments of the invention are directed to method of fabricating a semiconductor device. A non-limiting embodiment of the method includes performing fabrication operations to form a nanosheet field effect transistor (FET) device on a substrate, wherein the fabrication operations include forming gate spacers along a gate region of the nanosheet FET device, wherein each of the gate spacers comprises an upper segment and a lower segment.

公开(公告)号：US10566444B2

公开(公告)日：2020-02-18

申请号：US15850723

申请日：2017-12-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chen Zhang ,  Kangguo Cheng ,  Xin Miao ,  Wenyu Xu

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8234 ,  H01L29/06

Abstract: A method of forming a vertical fin field effect device is provided. The method includes, forming a vertical fin on a substrate, forming a masking block on the vertical fin, wherein the masking block extends a distance outward from the vertical fin sidewalls and endwalls, and a portion of the substrate surrounding the masking block is exposed. The method further includes removing at least a portion of the exposed portion of the substrate to form a recess and a fin mesa below the vertical fin, removing a portion of the fin mesa to form an undercut recess below an overhanging portion of the masking block, forming a spacer layer on the masking block and in the undercut recess, and removing a portion of the spacer layer to form an undercut spacer in the undercut recess.

公开(公告)号：US20200052124A1

公开(公告)日：2020-02-13

申请号：US16059101

申请日：2018-08-09

Applicant: International Business Machines Corporation

Inventor： Xin Miao ,  Alexander Reznicek ,  Choonghyun Lee ,  Jingyun Zhang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L23/532

Abstract: A sacrificial inner dielectric spacer is formed on physically exposed sidewalls of each recessed semiconductor channel material nanosheet of a nanosheet material stack that further includes recessed sacrificial semiconductor material nanosheets that have an inner dielectric spacer formed on physically exposed sidewalls thereof. A local isolation region is then formed by selective epitaxial growth on a surface of a semiconductor substrate containing the nanosheet material stack. After forming the local isolation region, the sacrificial inner dielectric spacers are removed and a source/drain region is formed on the physically exposed surface of each recessed semiconductor channel material nanosheet. A portion of the source/drain structure is formed in a gap located between each neighboring pair of vertically spaced apart inner dielectric spacers.

公开(公告)号：US10559692B2

公开(公告)日：2020-02-11

申请号：US16560607

申请日：2019-09-04

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Xin Miao ,  Jingyun Zhang ,  Choonghyun Lee

IPC: H01L29/786 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/02 ,  H01L29/423 ,  H01L29/06 ,  H01L21/762 ,  H01L29/66

Abstract: A thin layer of lattice matched wide bandgap semiconductor material having semi-insulating properties is employed as an isolation layer between the substrate and a vertical stack of suspended semiconductor channel material nanosheets. The presence of such an isolation layer eliminates the parasitic leakage path between the source region and the drain region that typically occurs through the substrate, while not interfering with the CMOS device that is formed around the semiconductor channel material nanosheets.

公开(公告)号：US20200043916A1

公开(公告)日：2020-02-06

申请号：US16584813

申请日：2019-09-26

Applicant: International Business Machines Corporation

Inventor： Xin Miao ,  Chen Zhang ,  Kangguo Cheng ,  Juntao Li

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/786

Abstract: Techniques for forming VFETs with differing gate lengths are provided. In one aspect, a method for forming a VFET device includes: patterning fins in a substrate, wherein at least one of the fins includes a vertical fin channel of a FET1 and at least another one of the fins includes a vertical fin channel of a FET2; forming a bottom source and drain; forming bottom spacers on the bottom source and drain; forming gates surrounding the vertical fin channel of the FET1 and FET2; forming top spacers on the gate; and forming top source and drains at the tops of the fins by varying a positioning of the top source and drains relative to at least one of the vertical fin channel of the FET1 and the FET2 such that the FET1/FET2 have an effective gate length Lgate1/Lgate2, wherein Lgate1>Lgate2. A VFET device is also provided.

公开(公告)号：US20200043798A1

公开(公告)日：2020-02-06

申请号：US16596570

申请日：2019-10-08

Applicant: International Business Machines Corporation

Inventor： Xin Miao ,  Kangguo Cheng ,  Chen Zhang

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L27/088

Abstract: Techniques for forming VFETs with differing gate lengths Lg on the same wafer using a gas cluster ion beam (GCIB) process to produce fins of differing heights are provided. In one aspect, a method of forming fins having different heights includes: patterning the fins having a uniform height in a substrate, the fins including at least one first fin and at least one second fin; forming an oxide at a base of the at least one second fin using a low-temperature directional oxidation process (e.g., GCIB oxidation); and removing the oxide from the base of the at least one second fin to reveal the at least one first fin having a height H1 and the at least one second fin having a height H2, wherein H2>H1. VFETs and methods for forming VFETs having different fin heights using this process are also provided.

公开(公告)号：US10522342B2

公开(公告)日：2019-12-31

申请号：US16002561

申请日：2018-06-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce B. Doris ,  Michael A. Guillorn ,  Isaac Lauer ,  Xin Miao

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/306 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.

公开(公告)号：US20190341496A1

公开(公告)日：2019-11-07

申请号：US15973043

申请日：2018-05-07

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Xin Miao ,  Jingyun Zhang ,  Choonghyun Lee

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8238

Abstract: A thin layer of lattice matched wide bandgap semiconductor material having semi-insulating properties is employed as an isolation layer between the substrate and a vertical stack of suspended semiconductor channel material nanosheets. The presence of such an isolation layer eliminates the parasitic leakage path between the source region and the drain region that typically occurs through the substrate, while not interfering with the CMOS device that is formed around the semiconductor channel material nanosheets.

公开(公告)号：US10446686B2

公开(公告)日：2019-10-15

申请号：US15916519

申请日：2018-03-09

Applicant: International Business Machines Corporation

Inventor： Terry Hook ,  Kangguo Cheng ,  Yi Song ,  Chen Zhang ,  Xin Miao ,  Peng Xu

IPC: H01L27/148 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088

Abstract: Techniques that facilitate an asymmetric dual gate fully depleted transistor are provided. In one example, a transistor device includes a semiconductor channel structure, a first gate structure and a second gate structure. The first gate structure comprises a first length. The second gate structure comprises a second length that is different than the first length. The first gate structure is disposed on a first surface of the semiconductor channel structure and the second gate structure is disposed on a second surface of the semiconductor channel structure.