公开(公告)号：US07323726B1

公开(公告)日：2008-01-29

申请号：US10658882

申请日：2003-09-09

申请人： Kuo-Tung Chang ,  Yu Sun

发明人： Kuo-Tung Chang ,  Yu Sun

IPC分类号： H01L29/76

CPC分类号： H01L29/0847 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11519 ,  H01L29/7881

摘要： A method and apparatus for coupling to a common line in an array. Gate structures of an integrated circuit are formed. Source and drain regions adjacent to the gate structures are implanted. A source contact from a metal Vss line to a source region is formed. Dopants of the source and drain regions diffuse laterally to overlap. The overlapping diffusion regions conduct and couple the drain region to a source region. Beneficially, the drain region is coupled to the metal Vss line. As a beneficial result, source contacts may be formed along a line of drain contacts in associated rows of drain contacts, and coupled to a common source line via the novel overlapping diffusion regions. A plurality of word lines may be formed without any bending in the word lines to accommodate source contacts that are larger than the source line. Numerous deleterious consequences of bent word lines, for example decreased array density and detrimental electrical behavior of memory cells in the vicinity of bent word lines, may beneficially be overcome by embodiments of the present invention.

摘要翻译： 一种用于耦合到阵列中的公共线的方法和装置。 形成集成电路的栅极结构。 植入与栅极结构相邻的源区和漏区。 形成从金属Vss线到源极区的源极接触。 源区和漏区的掺杂剂横向扩散以重叠。 重叠扩散区域将漏极区域导通并耦合到源极区域。 有利地，漏极区域耦合到金属Vss线。 作为有益的结果，源触点可以沿相关的漏极触点行中的漏极触点线形成，并且经由新颖的重叠扩散区域耦合到公共源极线。 可以形成多个字线，而不会在字线中任何弯曲以适应大于源极线的源极触点。 弯曲字线的许多有害后果，例如降低阵列密度，并且在弯曲字线附近的记忆单元的有害电气行为可有利地被本发明的实施例克服。

公开(公告)号：US20080012060A1

公开(公告)日：2008-01-17

申请号：US11458046

申请日：2006-07-17

申请人： Meng Ding ,  Amol Ramesh Joshi ,  Lei Xue ,  Takashi Orimoto ,  Kuo-Tung Chang

发明人： Meng Ding ,  Amol Ramesh Joshi ,  Lei Xue ,  Takashi Orimoto ,  Kuo-Tung Chang

IPC分类号： H01L29/76

CPC分类号： H01L27/11563 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/792

摘要： A memory cell system is provided forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming an intermediate layer over the charge trap layer, and forming a second insulator layer with the intermediate layer.

摘要翻译： 提供一种存储单元系统，在半导体衬底上形成第一绝缘体层，在第一绝缘体层上形成电荷陷阱层，在电荷陷阱层上形成中间层，并与中间层形成第二绝缘体层。

公开(公告)号：US07019366B1

公开(公告)日：2006-03-28

申请号：US10758173

申请日：2004-01-14

申请人： Nian Yang ,  Hiroyuki Ogawa ,  Yider Wu ,  Kuo-Tung Chang ,  Yu Sun

发明人： Nian Yang ,  Hiroyuki Ogawa ,  Yider Wu ,  Kuo-Tung Chang ,  Yu Sun

IPC分类号： H01L23/62

CPC分类号： H01L27/0251

摘要： More efficient use of silicon area is achieved by incorporating an electrostatic discharge protective (ESDP) device beneath a pad area of a semiconductor structure. The pad area includes a substrate having a first metal layer above it. A second metal layer is above the first metal layer. The ESDP device resides in the substrate below the first metal layer. A layer of dielectric separates the first and second metal layers. A via within the dielectric layer electrically couples the first and second metal layers. A via connects to the ESDP component. Subsequent metal layers can be arranged between the first and second metal layers. The Ohmic value of the resistance component of the ESDP device can be set during fabrication by fixing a number of individual via components, arranged electrically in parallel, by fixing the cross sectional area of the via components, and/or by fixing the length of the via components.

摘要翻译： 通过在半导体结构的焊盘区域的下方并入静电放电保护（ESDP）器件来实现硅面积的更有效的使用。 焊盘区域包括在其上方具有第一金属层的基板。 第二金属层位于第一金属层之上。 ESDP设备位于第一金属层下方的基板中。 电介质层分离第一和第二金属层。 电介质层内的通孔电耦合第一和第二金属层。 A通道连接到ESDP组件。 随后的金属层可以布置在第一和第二金属层之间。 ESDP装置的电阻部件的欧姆值可以在制造期间通过固定多个单独的通孔部件，通过固定通孔部件的横截面面积和/或固定长度 通过组件。

公开(公告)号：US06674138B1

公开(公告)日：2004-01-06

申请号：US10036757

申请日：2001-12-31

申请人： Arvind Halliyal ,  Mark T. Ramsbey ,  Kuo-Tung Chang ,  Nicholas H. Tripsas ,  Robert B. Ogle

发明人： Arvind Halliyal ,  Mark T. Ramsbey ,  Kuo-Tung Chang ,  Nicholas H. Tripsas ,  Robert B. Ogle

IPC分类号： H01L2976

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/7923

摘要： A process for fabrication of a semiconductor device including a modified ONO structure, including forming the modified ONO structure by providing a semiconductor substrate; forming a first oxide layer on the semiconductor substrate; depositing a layer comprising a high-K dielectric material on the first oxide layer; and forming a top oxide layer on the layer comprising a high-K dielectric material. The semiconductor device may be, e.g., a MIRRORBIT™ two-bit EEPROM device or a floating gate flash device including a modified ONO structure.

摘要翻译： 一种制造包括改性ONO结构的半导体器件的方法，包括通过提供半导体衬底形成修饰的ONO结构; 在所述半导体衬底上形成第一氧化物层; 在所述第一氧化物层上沉积包含高K电介质材料的层; 以及在包含高K电介质材料的层上形成顶部氧化物层。 半导体器件可以是例如MIRRORBIT TM 2位EEPROM器件或包括修改的ONO结构的浮动栅极闪存器件。

公开(公告)号：US06295229B1

公开(公告)日：2001-09-25

申请号：US09351742

申请日：1999-07-08

申请人： Kuo-Tung Chang ,  Erwin J. Prinz ,  Craig T. Swift

发明人： Kuo-Tung Chang ,  Erwin J. Prinz ,  Craig T. Swift

IPC分类号： G11C1604

CPC分类号： G11C16/0433 ,  G11C16/12

摘要： A semiconductor device (70) includes a memory cell having a select transistor (67) and a storage transistor (65) having a relatively uniform tunnel dielectric thickness under both the floating gate (651) of the storage transistor and the select gate (671) of the select transistor (67). The select transistor (67) is adjacent to the drain region (68) for the memory cell to nearly eliminate a drain disturb problem. During programming, the control gate (652) is at a negative potential, and the drain region (68) is at a positive potential. The drain potential is sufficiently low to not degrade the tunnel dielectric layer (42) of the select transistor (67). During erase, a positive potential is applied to the control gate (652). The relatively uniform tunnel dielectric layer (42) thickness of the select transistor (67) allows for a faster operating device by increasing the read current of the memory device.

摘要翻译： 半导体器件（70）包括具有在存储晶体管的浮动栅极（651）和选择栅极（671）两者下具有相对均匀的隧道电介质厚度的选择晶体管（67）和存储晶体管（65）的存储单元， 的选择晶体管（67）。 选择晶体管（67）与用于存储单元的漏极区域（68）相邻，几乎消除了漏极干扰问题。 在编程期间，控制栅极（652）处于负电位，漏区（68）处于正电位。 漏极电位足够低以不降低选择晶体管（67）的隧道介电层（42）。 在擦除期间，向控制栅极施加正电位（652）。 选择晶体管（67）的相对均匀的隧道介电层（42）的厚度通过增加存储器件的读取电流而允许更快的操作器件。

公开(公告)号：US5414693A

公开(公告)日：1995-05-09

申请号：US269972

申请日：1994-07-01

申请人： Yueh Y. Ma ,  Kuo-Tung Chang

发明人： Yueh Y. Ma ,  Kuo-Tung Chang

IPC分类号： H01L21/8247 ,  G11C11/56 ,  G11C16/04 ,  H01L27/115 ,  H01L29/68 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  G11C11/5621 ,  G11C16/0458

摘要： An EEPROM cell structure includes two floating gate transistors separated by a select gate transistor with the select transistor being shared by the two floating gate transistors in programming, reading, and erasing a floating gate transistor. The floating gates of the two transistors are formed from a first polysilicon layer, the control gates of the two transistors are formed from a second polysilicon layer, and the select gate is formed from a third doped polysilicon layer. The channel length of the select gate transistor is fully self-aligned to the floating gate transistors. A word line is formed over the control gates and forms the select gate. The word line runs generally perpendicular to bit lines which contact the drain regions of the two floating gate transistors. Accordingly, a virtual ground flash EEPROM memory array can be fabricated using the EEPROM cell structure.

摘要翻译： EEPROM单元结构包括由选择栅极晶体管隔开的两个浮栅晶体管，在编程，读取和擦除浮栅晶体管时，选择晶体管由两个浮栅晶体管共享。 两个晶体管的浮置栅极由第一多晶硅层形成，两个晶体管的控制栅极由第二多晶硅层形成，并且选择栅极由第三掺杂多晶硅层形成。 选择栅极晶体管的沟道长度与浮置栅极晶体管完全自对准。 在控制门上形成一条字线，形成选择门。 字线通常垂直于与两个浮栅晶体管的漏极区接触的位线。 因此，可以使用EEPROM单元结构来制造虚拟地闪存EEPROM存储器阵列。