公开(公告)号：US06295229B1

公开(公告)日：2001-09-25

申请号：US09351742

申请日：1999-07-08

申请人： Kuo-Tung Chang ,  Erwin J. Prinz ,  Craig T. Swift

发明人： Kuo-Tung Chang ,  Erwin J. Prinz ,  Craig T. Swift

IPC分类号： G11C1604

CPC分类号： G11C16/0433 ,  G11C16/12

摘要： A semiconductor device (70) includes a memory cell having a select transistor (67) and a storage transistor (65) having a relatively uniform tunnel dielectric thickness under both the floating gate (651) of the storage transistor and the select gate (671) of the select transistor (67). The select transistor (67) is adjacent to the drain region (68) for the memory cell to nearly eliminate a drain disturb problem. During programming, the control gate (652) is at a negative potential, and the drain region (68) is at a positive potential. The drain potential is sufficiently low to not degrade the tunnel dielectric layer (42) of the select transistor (67). During erase, a positive potential is applied to the control gate (652). The relatively uniform tunnel dielectric layer (42) thickness of the select transistor (67) allows for a faster operating device by increasing the read current of the memory device.

摘要翻译： 半导体器件（70）包括具有在存储晶体管的浮动栅极（651）和选择栅极（671）两者下具有相对均匀的隧道电介质厚度的选择晶体管（67）和存储晶体管（65）的存储单元， 的选择晶体管（67）。 选择晶体管（67）与用于存储单元的漏极区域（68）相邻，几乎消除了漏极干扰问题。 在编程期间，控制栅极（652）处于负电位，漏区（68）处于正电位。 漏极电位足够低以不降低选择晶体管（67）的隧道介电层（42）。 在擦除期间，向控制栅极施加正电位（652）。 选择晶体管（67）的相对均匀的隧道介电层（42）的厚度通过增加存储器件的读取电流而允许更快的操作器件。

公开(公告)号：US5981340A

公开(公告)日：1999-11-09

申请号：US939397

申请日：1997-09-29

申请人： Kuo-Tung Chang ,  Erwin J. Prinz ,  Craig T. Swift

发明人： Kuo-Tung Chang ,  Erwin J. Prinz ,  Craig T. Swift

IPC分类号： G11C16/04 ,  H01L27/115 ,  H01L21/336

CPC分类号： H01L27/115 ,  G11C16/0433

摘要： A semiconductor device (70) includes a memory cell having a select transistor (67) and a storage transistor (65) having a relatively uniform tunnel dielectric thickness under both the floating gate (651) of the storage transistor and the select gate (671) of the select transistor (67). The select transistor (67) is adjacent to the drain region (68) for the memory cell to nearly eliminate a drain disturb problem. During programming, the control gate (652) is at a negative potential, and the drain region (68) is at a positive potential. The drain potential is sufficiently low to not degrade the tunnel dielectric layer (42) of the select transistor (67). During erase, a positive potential is applied to the control gate (652). The relatively uniform tunnel dielectric layer (42) thickness of the select transistor (67) allows for a faster operating device by increasing the read current of the memory device.

摘要翻译： 半导体器件（70）包括具有在存储晶体管的浮动栅极（651）和选择栅极（671）两者下具有相对均匀的隧道电介质厚度的选择晶体管（67）和存储晶体管（65）的存储单元， 的选择晶体管（67）。 选择晶体管（67）与用于存储单元的漏极区域（68）相邻，几乎消除了漏极干扰问题。 在编程期间，控制栅极（652）处于负电位，漏区（68）处于正电位。 漏极电位足够低以不降低选择晶体管（67）的隧道介电层（42）。 在擦除期间，向控制栅极施加正电位（652）。 选择晶体管（67）的相对均匀的隧道介电层（42）的厚度通过增加存储器件的读取电流而允许更快的操作器件。

公开(公告)号：US07160775B2

公开(公告)日：2007-01-09

申请号：US10912825

申请日：2004-08-06

申请人： Erwin J. Prinz ,  Ramachandran Muralidhar ,  Rajesh A. Rao ,  Michael A. Sadd ,  Robert F. Steimle ,  Craig T. Swift ,  Bruce E. White

发明人： Erwin J. Prinz ,  Ramachandran Muralidhar ,  Rajesh A. Rao ,  Michael A. Sadd ,  Robert F. Steimle ,  Craig T. Swift ,  Bruce E. White

IPC分类号： H01L21/336

CPC分类号： B82Y10/00 ,  G11C16/0475 ,  G11C16/14 ,  G11C2216/06 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332

摘要： In one embodiment, a method for discharging a semiconductor device includes providing a semiconductor substrate, forming a hole blocking dielectric layer over the semiconductor substrate, forming nanoclusters over the hole blocking dielectric layer, forming a charge trapping layer over the nanoclusters, and applying an electric field to the nanoclusters to discharge the semiconductor device. Applying the electric field may occur while applying ultraviolet (UV) light. In one embodiment, the hole blocking dielectric layer comprises forming the hole blocking dielectric layer having a thickness greater than approximately 50 Angstroms.

摘要翻译： 在一个实施例中，一种用于放电半导体器件的方法包括提供半导体衬底，在半导体衬底上形成空穴阻挡电介质层，在空穴阻挡介电层上形成纳米团簇，在纳米团簇上形成电荷俘获层，并施加电 场到纳米团簇放电半导体器件。 施加紫外线（UV）光时可能会发生电场。 在一个实施例中，空穴阻挡介电层包括形成厚度大于约50埃的空穴阻挡介电层。

公开(公告)号：US06791883B2

公开(公告)日：2004-09-14

申请号：US10178658

申请日：2002-06-24

申请人： Craig T. Swift ,  Jane A. Yater ,  Alexander B. Hoefler ,  Ko-Min Chang ,  Erwin J. Prinz ,  Bruce L. Morton

发明人： Craig T. Swift ,  Jane A. Yater ,  Alexander B. Hoefler ,  Ko-Min Chang ,  Erwin J. Prinz ,  Bruce L. Morton

IPC分类号： G11C1600

CPC分类号： G11C16/0466

摘要： A non-volatile memory having a thin film dielectric storage element is programmed by hot carrier injection (HCI) and erased by tunneling. The typical structure for the memory cells for this type of memory is silicon, oxide, nitride, oxide, and silicon (SONOS). The hot carrier injection provides relatively fast programming for SONOS, while the tunneling provides for erase that avoids the difficulties with the hot hole erase (HHE) type erase that generally accompanies hot carrier injection for programming. HHE is significantly more damaging to dielectrics leading to reliability issues. HHE also has a relatively narrow area of erasure that may not perfectly match the pattern for the HCI programming leaving an incomplete erasure. The tunnel erase effectively covers the entire area so there is no concern about incomplete erase. Although tunnel erase is slower than HHE, erase time is generally less critical in a system operation than is programming time.

摘要翻译： 具有薄膜电介质存储元件的非易失性存储器通过热载流子注入（HCI）编程并通过隧道擦除。 这种存储器的存储单元的典型结构是硅，氧化物，氮化物，氧化物和硅（SONOS）。 热载波注入为SONOS提供相对快速的编程，而隧道提供擦除，避免了通常伴随热载流子注入进行编程的热孔擦除（HHE）类型擦除的困难。 HHE对电介质的破坏性更大，导致可靠性问题。 HHE还具有相对较窄的擦除区域，可能不完全匹配HCI编程的模式，从而导致不完整的擦除。 隧道擦除有效地覆盖整个区域，所以不用担心不完全擦除。 虽然隧道擦除比HHE慢，但擦除时间在系统操作中通常不如编程时间那么重要。

公开(公告)号：US06898129B2

公开(公告)日：2005-05-24

申请号：US10280294

申请日：2002-10-25

申请人： Craig T. Swift ,  Frank K. Baker, Jr. ,  Erwin J. Prinz ,  Paul A. Ingersoll

发明人： Craig T. Swift ,  Frank K. Baker, Jr. ,  Erwin J. Prinz ,  Paul A. Ingersoll

IPC分类号： G11C16/04 ,  G11C16/14

CPC分类号： G11C16/14 ,  G11C16/0466

摘要： A non volatile memory includes a plurality of transistors having a non conductive storage medium. The transistors are erased by injecting holes into the storage medium from both the source edge region and drain edge region of the transistor. In one example, the storage medium is made from silicon nitride isolated from the underlying substrate and overlying gate by silicon dioxide. The injection of holes in the storage medium generates two hole distributions having overlapping portions. The combined distribution of the overlapping portions is above at least a level of the highest concentration of program charge in the overlap region of the storage medium. In one example, the transistors are programmed by hot carrier injection. In some examples, the sources of groups of transistors of the memory are decoded.

摘要翻译： 非易失性存储器包括具有非导电存储介质的多个晶体管。 晶体管通过从晶体管的源极边缘区域和漏极边缘区域两端向存储介质注入空穴而被擦除。 在一个示例中，存储介质由从下面的衬底隔离并由二氧化硅覆盖的栅极制成。 在存储介质中注入孔产生具有重叠部分的两个孔分布。 重叠部分的组合分布高于存储介质的重叠区域中程序电荷的最高浓度的至少一个水平。 在一个示例中，通过热载流子注入对晶体管进行编程。 在一些示例中，解码存储器的晶体管组的源。

公开(公告)号：US06751125B2

公开(公告)日：2004-06-15

申请号：US10287328

申请日：2002-11-04

申请人： Erwin J. Prinz ,  Craig T. Swift ,  Jane A. Yater ,  Sung-Wei Lin ,  Frank K. Baker, Jr.

发明人： Erwin J. Prinz ,  Craig T. Swift ,  Jane A. Yater ,  Sung-Wei Lin ,  Frank K. Baker, Jr.

IPC分类号： G11C1604

CPC分类号： G11C16/3427 ,  G11C16/26 ,  G11C16/3418

摘要： A technique for reducing the read gate voltage in a memory array including memory cells having a transistor for storing charge indicative of the value stored in the cell. In one example, a voltage greater than the substrate voltage is applied to the sources of the transistors of the memory cells of the array to increase the threshold voltage of a transistor due the body effect. The read gate voltage is greater than the source voltage which is greater than the substrate voltage. A non read voltage of less than the source voltage is applied to the gates of the transistors of the unselected rows to reduce leakage current. With this embodiment, the threshold voltages of transistors having an erased state can be less than 0V. With some embodiments, the read disturb caused by a gate voltage can be reduced due to the reduction in the gate voltage. In other examples, a negative voltage is applied to the gates of unselected rows to prevent leakage current. Accordingly, the voltage thresholds of transistors having an erased state can be reduced, wherein the read gate voltage can be reduced as well.

摘要翻译： 一种用于降低存储器阵列中的读栅极电压的技术，包括具有用于存储指示存储在单元中的值的电荷的晶体管的存储单元。 在一个示例中，大于衬底电压的电压被施加到阵列的存储器单元的晶体管的源极，以增加由于体效应引起的晶体管的阈值电压。 读栅极电压大于比基板电压大的源极电压。 小于源极电压的非读取电压被施加到未选择行的晶体管的栅极以减少泄漏电流。 利用本实施例，具有擦除状态的晶体管的阈值电压可以小于0V。 利用一些实施例，由于栅极电压的降低可以降低由栅极电压引起的读取干扰。 在其他示例中，负电压施加到未选择的行的栅极以防止漏电流。 因此，可以减少具有擦除状态的晶体管的电压阈值，其中读取栅极电压也可以减小。

公开(公告)号：US07732278B2

公开(公告)日：2010-06-08

申请号：US12254294

申请日：2008-10-20

申请人： Erwin J. Prinz ,  Michael A. Sadd ,  Robert F. Steimle

发明人： Erwin J. Prinz ,  Michael A. Sadd ,  Robert F. Steimle

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L29/42328 ,  H01L29/42332

摘要： A split gate memory cell has a select gate, a control gate, and a charge storage structure. The select gate includes a first portion located over the control gate and a second portion not located over the control gate. In one example, the first portion of the select gate has a sidewall aligned with a sidewall of the control gate and aligned with a sidewall of the charge storage structure. In one example, the control gate has a p-type conductivity. In one example, the gate can be programmed by a hot carrier injection operation and can be erased by a tunneling operation.

摘要翻译： 分离栅极存储单元具有选择栅极，控制栅极和电荷存储结构。 选择栅极包括位于控制栅极上方的第一部分和不位于控制栅极上方的第二部分。 在一个示例中，选择栅极的第一部分具有与控制栅极的侧壁对齐并与电荷存储结构的侧壁对准的侧壁。 在一个示例中，控制栅极具有p型导电性。 在一个示例中，门可以通过热载流子注入操作来编程，并且可以通过隧道操作来擦除。

公开(公告)号：US20080261367A1

公开(公告)日：2008-10-23

申请号：US11738003

申请日：2007-04-20

申请人： Erwin J. Prinz ,  Mehul D. Shroff

发明人： Erwin J. Prinz ,  Mehul D. Shroff

IPC分类号： H01L21/8232

CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/7833

摘要： A method for making a semiconductor device having non-volatile memory cell transistors and transistors of another type is provided. In the method, a substrate is provided having an NVM region, a high voltage (HV) region, and a low voltage (LV) region. The method includes forming a gate dielectric layer on the HV and LV regions. A tunnel oxide layer is formed over the substrate in the NVM region and the gate dielectric in the HV and LV regions. A first polysilicon layer is formed over the tunnel dielectric layer and gate dielectric layer. The first polysilicon layer is patterned to form NVM floating gates. An ONO layer is formed over the first polysilicon layer. A single etch removal step is used to form gates for the HV transistors from the first polysilicon layer while removing the first polysilicon layer from the LV region.

摘要翻译： 提供一种制造具有非易失性存储单元晶体管和另一种晶体管的半导体器件的方法。 在该方法中，提供具有NVM区域，高电压（HV）区域和低电压（LV））区域的衬底。 该方法包括在HV和LV区域上形成栅极电介质层。 隧道氧化物层形成在NVM区域中的衬底上，HV和LV区域中的栅极电介质。 第一多晶硅层形成在隧道介电层和栅介质层上。 图案化第一多晶硅层以形成NVM浮动栅极。 在第一多晶硅层上形成ONO层。 单个蚀刻去除步骤用于从第一多晶硅层形成用于HV晶体管的栅极，同时从LV区域移除第一多晶硅层。

公开(公告)号：US06816414B1

公开(公告)日：2004-11-09

申请号：US10631142

申请日：2003-07-31

申请人： Erwin J. Prinz

发明人： Erwin J. Prinz

IPC分类号： G11C1604

CPC分类号： B82Y10/00 ,  G11C16/0425 ,  G11C16/0458 ,  G11C16/0491 ,  G11C16/14 ,  G11C2216/06 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7887

摘要： A method of discharging a charge storage location of a transistor of a non-volatile memory includes applying first and second voltages to a control gate and a well region, respectively, of the transistor. The first voltage is applied to the control gate of the transistor, wherein the control gate has at least a portion located adjacent to a select gate of the transistor. The transistor includes a charge storage location having nanoclusters disposed within dielectric material of a structure of the transistor located below the control gate. Lastly, a second voltage is applied to the well region located below the control gate. Applying the first voltage and the second voltage generates a voltage differential across the structure for discharging electrons from the nanoclusters of the charge storage location.

公开(公告)号：US20100240156A1

公开(公告)日：2010-09-23

申请号：US12405308

申请日：2009-03-17

申请人： Mohammed Suhail ,  Ko-Min Chang ,  Peter J. Kuhn ,  Erwin J. Prinz

发明人： Mohammed Suhail ,  Ko-Min Chang ,  Peter J. Kuhn ,  Erwin J. Prinz

IPC分类号： H01L21/66

CPC分类号： G11C29/06 ,  G11C16/04 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50016 ,  G11C2029/0403

摘要： Testing a non volatile memory by exposing the non volatile memory to particle radiation (e.g. xenon ions) to emulate memory cell damage due to data state changing events of a non volatile memory cell. After the exposing, the memory cells are subjected to tests and the results of the tests are used to develop reliability indications of the non volatile memory. Integrated circuits with non volatile memories of the same design are provided. Reliability representations of the integrated circuits can be made with respect to a number of data state charging events based on the exposure and subsequent tests.

摘要翻译： 通过将非易失性存储器暴露于粒子辐射（例如氙离子）来测试非易失性存储器，以模拟由非易失性存储器单元的数据状态改变事件引起的存储器单元损坏。 在曝光之后，对存储器单元进行测试，并且测试结果用于开发非易失性存储器的可靠性指示。 提供了具有相同设计的非易失性存储器的集成电路。 集成电路的可靠性表示可以基于曝光和随后的测试相对于多个数据状态充电事件进行。