公开(公告)号：US20190156893A1

公开(公告)日：2019-05-23

申请号：US15816484

申请日：2017-11-17

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee

IPC: G11C16/08 ,  G11C16/04

Abstract: Memory device having a tile architecture are disclosed. The memory device may include a first plane having multiple pairs of tiles, wherein at least some of the pairs of tiles of the first plane include a distributed block select circuit and page buffer circuitry. Another memory device may include a memory array, and a CMOS under array region. At least some tile regions may include portions of a total amount of block select circuitry distributed throughout the CUA region, vertical string drivers located outside of the memory array, and page buffer circuitry coupled with the memory array. Another memory device may include a first tile pair including a first tile, a second tile, a first vertical string driver therebetween, a first page buffer region that is greater than 50% of area for the first tile pair, and a first portion of a distributed block select circuitry.

公开(公告)号：US09460803B1

公开(公告)日：2016-10-04

申请号：US14864990

申请日：2015-09-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Qiang Tang ,  Ali Feiz Zarrin Ghalam ,  Hoon Choi ,  Eric N. Lee ,  Ramin Ghodsi

IPC: G11C16/26 ,  G11C7/22 ,  G11C16/32 ,  G11C7/10 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C5/063 ,  G11C7/04 ,  G11C7/08 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/222 ,  G11C16/0483 ,  G11C16/32

Abstract: A system includes a plurality of sensing devices, a first multiplexer, a plurality of local return clock signal paths, a second multiplexer, and a data latch. Each sensing device outputs data onto a respective local data path in response to a clock signal on a clock signal path. The first multiplexor passes data from a selected local data path to a global data path. Each local return clock signal path is coupled to the clock signal path at a respective sensing device such that each local return clock signal path is routed along with a respective local data path. The second multiplexor passes a return clock signal from a selected local return clock signal path corresponding to the selected local data path to a global return clock signal path. The data latch latches the data on the global data path into the data latch in response to the return clock signal on the global return clock signal path.

Abstract translation: 系统包括多个感测装置，第一多路复用器，多个本地返回时钟信号路径，第二多路复用器和数据锁存器。 每个感测装置响应于时钟信号路径上的时钟信号将数据输出到相应的本地数据路径上。 第一多路复用器将数据从选定的本地数据路径传递到全局数据路径。 每个本地返回时钟信号路径在相应感测装置处耦合到时钟信号路径，使得每个本地返回时钟信号路径与相应的本地数据路径一起路由。 第二多路复用器将来自对应于所选择的本地数据路径的选择的本地返回时钟信号路径的返回时钟信号传递到全局返回时钟信号路径。 响应于全局返回时钟信号路径上的返回时钟信号，数据锁存器将全局数据通路上的数据锁存到数据锁存器中。

公开(公告)号：US09190133B2

公开(公告)日：2015-11-17

申请号：US13793347

申请日：2013-03-11

Applicant: Micron Technology, Inc.

Inventor： Dean K. Nobunaga ,  Ali Feiz Zarrin Ghalam ,  Xiaojiang Guo ,  Eric N. Lee

IPC: G06F12/00 ,  G11C11/00 ,  G06F12/08

CPC classification number: G06F3/0629 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0683 ,  G06F12/0802 ,  G06F12/0893 ,  G06F13/1684 ,  G06F13/4068 ,  G06F2212/1016 ,  G06F2212/3042 ,  G11C5/066 ,  G11C7/1048 ,  G11C8/12 ,  G11C11/00

Abstract: Apparatuses and methods for reducing capacitance on a data bus are disclosed herein. In accordance with one or more described embodiments, an apparatus may comprise a plurality of memories coupled to an internal data bus and a command and address bus, each of the memories configured to receive a command on the command and address bus. One of the plurality of memories may be coupled to an external data bus. The one of the plurality of memories may be configured to provide program data to the internal data bus when the command comprises a program command and another of the plurality of memories is a target memory of the program command and may be configured to provide read data to the external data bus when the command comprises a read command and the another of the plurality of memories is a target memory of the read command.

Abstract translation: 本文公开了用于减小数据总线上的电容的装置和方法。 根据一个或多个所描述的实施例，装置可以包括耦合到内部数据总线和命令和地址总线的多个存储器，每个存储器被配置为在命令和地址总线上接收命令。 多个存储器中的一个可以耦合到外部数据总线。 多个存储器中的一个可以被配置为当命令包括程序命令时向内部数据总线提供程序数据，并且多个存储器中的另一个是程序命令的目标存储器，并且可以被配置为将读取数据提供给 当命令包括读取命令并且多个存储器中的另一个是读取命令的目标存储器时的外部数据总线。