公开(公告)号：US20210217471A1

公开(公告)日：2021-07-15

申请号：US16771657

申请日：2019-12-03

Applicant: Micron Technology , Inc.

Inventor： Umberto Di Vincenzo ,  Riccardo Muzzetto ,  Ferdinando Bedeschi

IPC: G11C13/00

Abstract: The present disclosure relates to a method for reading memory cells, comprising the steps of applying a first read voltage to a plurality of memory cells, detecting first threshold voltages exhibited by the plurality of memory cells in response to application of the first read voltage, based on the first threshold voltages, associating a first logic state to one or more cells of the plurality of memory cells, applying a second read voltage to the plurality of memory cells, wherein the second read voltage has the same polarity of the first read voltage and a higher magnitude than an expected highest threshold voltage of memory cells in the first logic state, detecting second threshold voltages exhibited by the plurality of memory cells in response to application of the second read voltage, based on the second threshold voltages, associating a second logic state to one or more cells of the plurality of memory cells, applying a third read voltage to the plurality of memory cells, wherein the third read voltage has the same polarity of the first and second read voltages and is applied at least to a group of memory cells that, during the application the second read voltage, have been reprogrammed to an opposite logic state, detecting third threshold voltages exhibited by the plurality of memory cells in response to application of the third read voltage, and based on the third threshold voltages, associating one of the first or second logic state to one or more of the cells of the of the plurality of memory cells. A related circuit, a related memory device and a related system are also disclosed.

公开(公告)号：US20210217470A1

公开(公告)日：2021-07-15

申请号：US16771177

申请日：2019-12-03

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Riccardo Muzzetto ,  Ferdinando Bedeschi

IPC: G11C13/00

Abstract: The present disclosure provides a method, a circuit, and a system for reading memory cells. The method comprises: applying a first voltage with a first polarity to a plurality of the memory cells; applying a second voltage with a second polarity to one or more of said plurality of the memory cells; applying at least a third voltage with the first polarity to one or more of said plurality of the memory cells; detecting electrical responses of memory cells to the first voltage, the second voltage, and the third voltage; and determining a logic state of respective memory cells based on the electrical responses of the memory cells to the first voltage, the second voltage, and the third voltage.

公开(公告)号：US11056178B1

公开(公告)日：2021-07-06

申请号：US16933829

申请日：2020-07-20

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo ,  Riccardo Muzzetto ,  Angelo Visconti

IPC: G11C7/06 ,  G11C11/4091 ,  G11C11/4074 ,  G11C11/404 ,  G11C11/4099 ,  G11C11/22 ,  G11C11/24

Abstract: Methods, systems, and devices for read operations based on a dynamic reference are described. A memory device may include a set of memory cells each associated with a capacitive circuit including a first and second capacitor. After receiving a read command, the memory device may couple each capacitive circuit with a respective memory cell (e.g., to transfer a charge stored by each respective memory cell to a capacitive circuit) and may couple the second capacitor of each capacitive circuit to a reference voltage bus. Thus, a reference voltage on the reference voltage bus may be based on an average charge across the second capacitors of each capacitive circuit. The memory device may then compare a charge stored by the first and second capacitors of each capacitive circuit with the reference voltage bus and may output a set of values stored by the set of memory cells based on the comparing.

公开(公告)号：US20210125655A1

公开(公告)日：2021-04-29

申请号：US17091580

申请日：2020-11-06

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Ferdinando Bedeschi

IPC: G11C11/22

Abstract: Methods, systems, and apparatuses for full bias sensing in a memory array are described. Various embodiments of an access operation of a cell in a array may be timed to allow residual charge of a middle electrode between the cell and a selection component to discharge. Access operations may also be timed to allow residual charge of middle electrodes associated with other cells to be discharged. In conjunction with an access operation for a target cell, a residual charge of a middle electrode of another cell may be discharged, and the target cell may then be accessed. A capacitor in electronic communication with a cell may be charged and a logic state of the cell determined based on the charge of the capacitor. The timing for charging the capacitor may be related to the time for discharging a middle electrode of the cell or another cell.

公开(公告)号：US10943656B2

公开(公告)日：2021-03-09

申请号：US16419845

申请日：2019-05-22

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Simone Lombardo

IPC: G11C13/00 ,  G11C11/56

Abstract: Apparatus and methods utilize a replica circuit to generate a voltage for programming of a memory cell, such as a memory cell of a phase-change memory (PCM). Current passing through a circuit including the memory cell to be programmed is mirrored in a scaled or unscaled manner, and provided as an input to the replica circuit. The replica circuit represents voltage drops that should be encountered when programming the memory cell. An input voltage is also provided to the replica circuit, which affects the voltage drop within the replica circuit that represents the voltage drop of the cell. The voltage drop across the replica circuit can then be mirrored and provided to bias the circuit including the memory cell.

公开(公告)号：US20210065763A1

公开(公告)日：2021-03-04

申请号：US16552984

申请日：2019-08-27

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Ferdinando Bedeschi ,  Riccardo Muzzetto

IPC: G11C11/22

Abstract: Methods, systems, and devices for word line timing management are described. In some examples, a digit line may be precharged as part of accessing a memory cell. The memory cell may include a storage component and a selection component. A word line may be coupled with the selection component, and the word line may be selected in order to couple the storage component with the digit line, by way of the selection component. The word line may be selected while the digit line is still being precharged, and the storage component may become coupled with the digit line with reduced delay after the end of precharging of the digit line, concurrent with the end of the precharging of the digit line, or while the digit line is still being charged. Related techniques for sensing a logic state stored by the memory cell are also described.

公开(公告)号：US10896710B2

公开(公告)日：2021-01-19

申请号：US16592630

申请日：2019-10-03

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo

IPC: G11C11/22 ,  G11C11/404 ,  G11C11/409 ,  G11C11/408 ,  G11C7/10 ,  G11C11/4091 ,  G11C7/06 ,  G11C5/14 ,  G11C27/02

Abstract: Methods, systems, and devices for operating a memory cell or cells are described. A capacitor coupled with an access line may be precharged and then boosted such that the charge stored in the capacitor is elevated to a higher voltage with respect to a memory cell. The boosted charge in the capacitor may support sensing operations that would otherwise require a relatively higher voltage. Some embodiments may employ charge amplification between an access line and a sense component, which may amplify signals between the memory cell and the sense component, and reduce charge sharing between these components. Some embodiments may employ “sample-and-hold” operations, which may re-use certain components of a sense component to separately generate a signal and a reference, reducing sensitivity to manufacturing and/or operational tolerances. In some embodiments, sensing may be further improved by employing “self-reference” operations that use a memory cell to generate its own reference.

公开(公告)号：US10854266B1

公开(公告)日：2020-12-01

申请号：US16523404

申请日：2019-07-26

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Ferdinando Bedeschi

IPC: G11C11/22

Abstract: Methods, systems, and apparatuses for full bias sensing in a memory array are described. Various embodiments of an access operation of a cell in a array may be timed to allow residual charge of a middle electrode between the cell and a selection component to discharge. Access operations may also be timed to allow residual charge of middle electrodes associated with other cells to be discharged. In conjunction with an access operation for a target cell, a residual charge of a middle electrode of another cell may be discharged, and the target cell may then be accessed. A capacitor in electronic communication with a cell may be charged and a logic state of the cell determined based on the charge of the capacitor. The timing for charging the capacitor may be related to the time for discharging a middle electrode of the cell or another cell.

公开(公告)号：US10714185B2

公开(公告)日：2020-07-14

申请号：US16168952

申请日：2018-10-24

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Umberto Di Vincenzo

IPC: G11C11/34 ,  G11C16/12 ,  G11C16/28 ,  G11C7/14 ,  G11C11/24 ,  G11C7/06 ,  G11C11/404 ,  G11C13/00 ,  G11C11/56

Abstract: A counter can have a number of sensing components. Each respective sensing component can be configured to sense a respective event and can include a respective first capacitor configured to be selectively coupled to a second capacitor in response to the respective sensing component sensing the respective event. The second capacitor can be configured to be charged to a voltage by each respective first capacitor that is selectively coupled to the second capacitor. The counter can have a comparator with a first input coupled to the second capacitor and a second input coupled to a reference voltage corresponding to a threshold quantity of events. The comparator can be configured to output a signal indicative of the threshold quantity of events being sensed in response to the voltage of the second capacitor being greater than or equal to the reference voltage.

公开(公告)号：US20200135276A1

公开(公告)日：2020-04-30

申请号：US16168952

申请日：2018-10-24

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Umberto Di Vincenzo

IPC: G11C16/12 ,  G11C16/28 ,  G11C11/404 ,  G11C11/24 ,  G11C7/06 ,  G11C7/14

Abstract: A counter can have a number of sensing components. Each respective sensing component can be configured to sense a respective event and can include a respective first capacitor configured to be selectively coupled to a second capacitor in response to the respective sensing component sensing the respective event. The second capacitor can be configured to be charged to a voltage by each respective first capacitor that is selectively coupled to the second capacitor. The counter can have a comparator with a first input coupled to the second capacitor and a second input coupled to a reference voltage corresponding to a threshold quantity of events. The comparator can be configured to output a signal indicative of the threshold quantity of events being sensed in response to the voltage of the second capacitor being greater than or equal to the reference voltage.