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公开(公告)号：US11527291B2
公开(公告)日：2022-12-13
申请号：US17062453
申请日：2020-10-02
发明人： Kishore Kumar Muchherla , Harish R. Singidi , Vamsi Pavan Rayaprolu , Ashutosh Malshe , Sampath K. Ratnam
摘要： A request to perform a secure erase operation for a memory component can be received. A voltage level that is applied to unselected wordlines of the memory component during a read operation can be determined. A voltage pulse can be applied to at least one wordline of the memory component to perform the secure erase operation. The voltage pulse can be associated with a program operation to place a memory cell of the memory component at another voltage level that exceeds the voltage level that is applied to the unselected wordlines of the memory component during the read operation.
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公开(公告)号：US11521699B2
公开(公告)日：2022-12-06
申请号：US17085445
申请日：2020-10-30
发明人： Vamsi Pavan Rayaprolu , Kishore Kumar Muchherla , Ashutosh Malshe , Gianni S. Alsasua , Harish R. Singidi
摘要： A first scan operation of a set of memory pages of a data block is performed using a first reliability threshold level to identify a set of scan results. A workload type associated with the data block is determined based on the set of scan results. The first reliability threshold level is adjusted to a second reliability threshold level based on the workload type. A second scan operation of the set of memory pages of the data block is performed using the second reliability threshold level.
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公开(公告)号：US11456051B1
公开(公告)日：2022-09-27
申请号：US17212531
申请日：2021-03-25
发明人： Gary F. Besinga , Renato C. Padilla , Tawalin Opastrakoon , Sampath K. Ratnam , Michael G. Miller , Christopher M. Smitchger , Vamsi Pavan Rayaprolu , Ashutosh Malshe
摘要： A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including receiving a set of read offsets for a block of the memory device, the set of read offsets comprising a default read offset, selecting the default read offset from the set of read offsets based on one or more criteria, applying the default read offset to a read operation performed with respect to the block, determining that a second set of criteria associated with removing the default read offset is satisfied, and removing the default read offset responsive to determining that the second set of criteria is satisfied.
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公开(公告)号：US11436078B2
公开(公告)日：2022-09-06
申请号：US17228425
申请日：2021-04-12
发明人： Harish Reddy Singidi , Xiangang Luo , Jianmin Huang , Kishore Kumar Muchherla , Ashutosh Malshe , Vamsi Pavan Rayaprolu , Sampath Ratnam
IPC分类号： G06F11/10 , G11C7/10 , G11C11/419 , G06F12/02
摘要： Disclosed in some examples are techniques for handling parity data of a non-volatile memory device with limited cache memory. In certain examples, user data can be programmed into the non-volatile memory of the non-volatile memory device in data stripes, and parity information can be calculated for each individual data stripe within a limited capacity cache of the non-volatile memory device. The individual parity information can be swapped between a swap block of the non-volatile memory and the limited capacity cache as additional data stripes are programmed.
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公开(公告)号：US20220188034A1
公开(公告)日：2022-06-16
申请号：US17552237
申请日：2021-12-15
IPC分类号： G06F3/06
摘要： A system includes a memory device and a processing device coupled to the memory device. The processing device can assign each of a plurality of superblocks to one of a plurality of groups. The processing device can monitor an order that each of the groups have been written to. The processing device can write data to a first block of a first superblock of a first of the plurality of groups.
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公开(公告)号：US20220179577A1
公开(公告)日：2022-06-09
申请号：US17681075
申请日：2022-02-25
发明人： Kishore Kumar Muchherla , Ashutosh Malshe , Vamsi Pavan Rayaprolu , Harish R. Singidi , Gianni S. Alsasua
摘要： A processing device in a memory system receives a first read request from a host system, wherein the first read request is directed to first data stored at a first address in a block of the memory component. The processing device determines that the first address is located within a first region of the block and increments a read counter for the block by a default amount. The processing device further receives a second read request from the host system, wherein the second read request is directed to second data stored at a second address in a block of the memory component, determines that the second address is located within a second region of the block and increments the read counter for the block by a scaled amount.
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公开(公告)号：US11354037B2
公开(公告)日：2022-06-07
申请号：US16947713
申请日：2020-08-13
发明人： Vamsi Pavan Rayaprolu , Sampath K. Ratnam , Harish R. Singidi , Ashutosh Malshe , Kishore Kumar Muchherla
IPC分类号： G06F3/06
摘要： A system includes a memory component and a processing device to determine an amount of data stored at a region of a memory component and determine, based on the amount of data stored in the region of the memory component. The processing device determines a frequency to perform an operation on one or more memory cells of the region of the memory component. The processing device performs the operation on the one or more memory cells at the frequency to maintain the one or more memory cells of the region of the memory component in a first state associated with a first error rate for data stored at the one or more memory cells. The first error rate is less than a second error rate associated with a second state of the one or more memory cells.
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公开(公告)号：US11334428B2
公开(公告)日：2022-05-17
申请号：US16989478
申请日：2020-08-10
发明人： Harish Reddy Singidi , Kishore Kumar Muchherla , Xiangang Luo , Vamsi Pavan Rayaprolu , Ashutosh Malshe
摘要： A variety of applications can include use of parity groups in a memory system with the parity groups arranged for data protection of the memory system. Each parity group can be structured with multiple data pages in which to write data and a parity page in which to write parity data generated from the data written in the multiple data pages. Each data page of a parity group can have storage capacity to include metadata of data written to the data page. Information can be added to the metadata of a data page with the information identifying an asynchronous power loss status of data pages that precede the data page in an order of writing data to the data pages of the parity group. The information can be used in re-construction of data in the parity group following an uncorrectable error correction code error in writing to the parity group.
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公开(公告)号：US20220068412A1
公开(公告)日：2022-03-03
申请号：US17453289
申请日：2021-11-02
发明人： Vamsi Pavan Rayaprolu , Giuseppina Puzzilli , Karl D. Schuh , Jeffrey S. McNeil, JR. , Kishore K. Muchherla , Ashutosh Malshe , Niccolo' Righetti
摘要： A first group of memory cells of a memory device can be subjected to a particular quantity of program/erase cycles (PECs) in response to a programming operation performed on a second group of memory cells of the memory device. Subsequent to subjecting the first group of memory cells to the particular quantity of PECs, a data retention capability of the first group of memory cells can be assessed.
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公开(公告)号：US20220019507A1
公开(公告)日：2022-01-20
申请号：US17492220
申请日：2021-10-01
发明人： Harish Reddy Singidi , Vamsi Pavan Rayaprolu , Kishore Kumar Muchherla , Jianmin Huang , Xiangang Luo , Ashutosh Malshe
摘要： A variety of applications can include apparatus and/or methods to preemptively detect defect prone memory blocks in a memory device and handle these memory blocks before they fail and trigger a data loss event. Metrics based on memory operations can be used to facililtate the examination of the memory blocks. One or more metrics associated with a memory operation on a block of memory can be tracked and a Z-score for each metric can be generated. In response to a comparison of a Z-score for a metric to a Z-score threshold for the metric, operations can be performed to control possible retirement of the memory block beginning with the comparison. Additional apparatus, systems, and methods are disclosed.
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