公开(公告)号：US20240267520A1

公开(公告)日：2024-08-08

申请号：US18640826

申请日：2024-04-19

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE ,  Ryuichi KANOH ,  Chong Soon LIM ,  Sughosh Pavan SHASHIDHAR ,  Ru Ling LIAO ,  Hai Wei SUN ,  Han Boon TEO ,  Jing Ya LI

IPC: H04N19/119 ,  H04N19/157 ,  H04N19/176

CPC classification number: H04N19/119 ,  H04N19/157 ,  H04N19/176

Abstract: An encoder partitions into blocks using a set of block partition modes. The set of block partition modes includes a first partition mode for partitioning a first block, and a second block partition mode for partitioning a second block which is one of blocks obtained after the first block is partitioned. When the number of partitions of the first block partition mode is three, the second block is a center block among the blocks obtained after partitioning the first block, and the partition direction of the second block partition mode is same as the partition direction of the first block partition mode, the second block partition mode indicates that the number of partitions is only three. A parameter for identifying the second block partition mode includes a first flag indicating a horizontal or vertical partition direction, and does not include a second flag indicating the number of partitions.

公开(公告)号：US20240223793A1

公开(公告)日：2024-07-04

申请号：US18438708

申请日：2024-02-12

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Yusuke KATO

IPC: H04N19/46 ,  H04N19/184 ,  H04N19/65

CPC classification number: H04N19/46 ,  H04N19/184 ,  H04N19/65

Abstract: An encoder that includes memory and circuitry coupled to the memory. The circuitry encodes a slice into one or more data access regions in a variable length encoding process. The circuitry encodes one or more offsets into a slice header, based on a flag written into a sequence header and a total number of the one or more data access regions. The one or more offsets each specify a head position of a corresponding one of the one or more data access regions in a bitstream. When the flag indicates that the one or more offsets are to be encoded and the total number is at least two, the one or more offsets are encoded. The flag switches between encoding and not encoding the one or more offsets regardless of whether the total number is at least two.

公开(公告)号：US20240214589A1

公开(公告)日：2024-06-27

申请号：US18435124

申请日：2024-02-07

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie DRUGEON ,  Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE ,  Yusuke KATO

IPC: H04N19/196 ,  H04N19/31 ,  H04N19/46 ,  H04N19/70

CPC classification number: H04N19/196 ,  H04N19/31 ,  H04N19/46 ,  H04N19/70

Abstract: An encoder includes memory and circuitry coupled to the memory. The circuitry, for each of temporal sub-layers for temporal scalability different from spatial scalability, stores first parameters into buffering period supplemental enhancement information (SEI) and encodes the first parameters. The first parameters present initial delays in timing to extract data from a coded picture buffer (CPB). The circuitry stores a second parameter into the buffering period SEI and encodes the second parameter. The second parameter indicates a total number of the temporal sub-layers. A value of the second parameter is equal to a value of a third parameter that is encoded into a sequence parameter set and indicates a total number of the temporal sub-layers.

公开(公告)号：US20240187622A1

公开(公告)日：2024-06-06

申请号：US18419347

申请日：2024-01-22

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Che-Wei KUO ,  Chong Soon LIM ,  Han Boon TEO ,  Jing Ya LI ,  Hai Wei SUN ,  Chu Tong WANG ,  Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE ,  Yusuke KATO

IPC: H04N19/44 ,  H04N19/105 ,  H04N19/117 ,  H04N19/13 ,  H04N19/159 ,  H04N19/176 ,  H04N19/186 ,  H04N19/46

CPC classification number: H04N19/44 ,  H04N19/105 ,  H04N19/117 ,  H04N19/13 ,  H04N19/159 ,  H04N19/176 ,  H04N19/186 ,  H04N19/46

Abstract: A decoder includes circuitry which, in operation, parses a first flag indicating whether a CCALF (cross component adaptive loop filtering) process is enabled for a first block located adjacent to a left side of a current block; parses a second flag indicating whether the CCALF process is enabled for a second block located adjacent to an upper side of the current block; determines a first index associated with a color component of the current block; and derives a second index indicating a context model, using the first flag, the second flag, and the first index. The circuitry, in operation, performs entropy decoding of a third flag indicating whether the CCALF process is enabled for the current block, using the context model indicated by the second index; and performs the CCALF process on the current block in response to the third flag indicating the CCALF process is enabled for the current block.

公开(公告)号：US20240187598A1

公开(公告)日：2024-06-06

申请号：US18441617

申请日：2024-02-14

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Yusuke KATO ,  Kiyofumi ABE ,  Tadamasa TOMA ,  Takahiro NISHI

IPC: H04N19/13 ,  H04N19/105 ,  H04N19/176 ,  H04N19/46 ,  H04N19/91

CPC classification number: H04N19/13 ,  H04N19/105 ,  H04N19/176 ,  H04N19/46 ,  H04N19/91

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In residual coding of a current block to which an orthogonal transform is not applied, when coefficient information flags relating to a coefficient in the current block are encoded, the circuitry: performs a level mapping process to transform the coefficient to a second coefficient by using a predicted value, in which the predicted value is determined based on neighboring coefficients of the coefficient within the current block; encodes second coefficient information flags by Context-based Adaptive Binary Arithmetic Coding (CABAC), each of the second coefficient information flags relating to the second coefficient; and encodes a remainder value of the coefficient with Golomb-Rice code, and when the coefficient information flags are not encoded, in operation, the circuitry: skips the level mapping process; and encodes a value of the coefficient with the Golomb-Rice code.

公开(公告)号：US20240129523A1

公开(公告)日：2024-04-18

申请号：US18545682

申请日：2023-12-19

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Ryuichi KANOH ,  Chong Soon LIM ,  Ru Ling LIAO ,  Hai Wei SUN ,  Sughosh Pavan SHASHIDHAR ,  Han Boon TEO ,  Jing Ya LI

IPC: H04N19/52 ,  H04N19/119 ,  H04N19/176

CPC classification number: H04N19/52 ,  H04N19/119 ,  H04N19/176

Abstract: An encoder includes circuitry and memory. Using the memory, the circuitry, in operation, selects an encoding mode from among candidates including a decoder-side motion vector refinement (DMVR) encoding mode and a partition encoding mode. When the DMVR encoding mode is selected, the circuitry: obtains a first motion vector for a first image block; derives a second motion vector from the first motion vector using motion search; and generates a prediction image for the first image block using the second motion vector. When the partition encoding mode is selected, the circuitry: determines a plurality of partitions in a second image block; obtains a third motion vector for each partition; and generates a prediction image for the second image block using the third motion vector, without deriving a fourth motion vector from the third motion vector using motion search.

公开(公告)号：US20240114134A1

公开(公告)日：2024-04-04

申请号：US18530032

申请日：2023-12-05

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Sughosh Pavan SHASHIDHAR ,  Hai Wei SUN ,  Chong Soon LIM ,  Ru Ling LIAO ,  Han Boon TEO ,  Jing Ya LI ,  Takahiro NISHI ,  Kiyofumi ABE ,  Ryuichi KANOH ,  Tadamasa TOMA

IPC: H04N19/119 ,  H04N19/176 ,  H04N19/184 ,  H04N19/60

CPC classification number: H04N19/119 ,  H04N19/176 ,  H04N19/184 ,  H04N19/60

Abstract: An encoder includes circuitry and a memory coupled to the circuitry. The circuitry, in operation, determines whether or not a ternary split process of splitting a block into three sub blocks in a first direction parallel to a first longer side of the block is allowed by comparing a size of a second shorter side of the block to a minimum threshold value. The circuitry, responsive to the ternary split process being allowed, writes, into a bitstream, a split direction parameter indicative of a splitting direction. The circuitry, in operation, splits the block into a plurality of sub blocks in a direction indicated by the split direction parameter; and encodes the plurality of sub blocks. The minimum threshold value corresponds to a minimum size supported in a transform process.

公开(公告)号：US20240104782A1

公开(公告)日：2024-03-28

申请号：US18533972

申请日：2023-12-08

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Takahiro NISHI ,  Toshiyasu Sugio ,  Noritaka Iguchi

IPC: G06T9/00 ,  H04N19/13 ,  H04N19/146

CPC classification number: G06T9/00 ,  H04N19/13 ,  H04N19/146

Abstract: A three-dimensional data encoding method includes: encoding, for each of second units, information about positions of three-dimensional points included in a first unit, to generate encoded data items, the second units being smaller than the first unit that is an encoding unit; and outputting the encoded data items. Each of the encoded data items includes no individual additional information. The encoded data items include common additional information. The common additional information includes first information indicating a size of a first encoded data item included in the encoded data items.

公开(公告)号：US20240098287A1

公开(公告)日：2024-03-21

申请号：US18515944

申请日：2023-11-21

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Takahiro NISHI ,  Tadamasa Toma ,  Kiyofumi Abe ,  Ryuichi Kanoh

IPC: H04N19/31 ,  H04N19/117 ,  H04N19/172

CPC classification number: H04N19/31 ,  H04N19/117 ,  H04N19/172

Abstract: An encoder which encodes a video including a plurality of pictures includes circuitry and memory. Using the memory, the circuitry performs: encoding a first picture among the plurality of pictures; and performing (i) a first operation for encoding a parameter set for a second picture which follows the first picture in coding order among the plurality of pictures after encoding the first picture, and encoding the second picture after encoding the parameter set, or (ii) a second operation for encoding the second picture without encoding the parameter set after encoding the first picture. The circuitry performs the first operation when the second picture is a determined picture, in the performing of the first operation or the second operation.

公开(公告)号：US20240048691A1

公开(公告)日：2024-02-08

申请号：US18489678

申请日：2023-10-18

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Ryuichi KANOH

IPC: H04N19/105 ,  H04N19/119 ,  H04N19/139 ,  H04N19/14 ,  H04N19/176 ,  H04N19/52 ,  H04N19/573

CPC classification number: H04N19/105 ,  H04N19/119 ,  H04N19/139 ,  H04N19/14 ,  H04N19/176 ,  H04N19/52 ,  H04N19/573

Abstract: A decoder includes circuitry and memory. Using the memory, the circuitry, in a first operating mode, derives first motion vectors for a first block obtained by splitting a picture, using a first inter prediction scheme, and generates a prediction image corresponding to the first block, by referring to spatial gradients of luminance generated based on the first motion vectors. Using the memory, the circuitry, in a second operating mode, derives second motion vectors for a sub-block obtained by splitting a second block, using a second inter prediction scheme different from the first inter prediction scheme, the second block being obtained by splitting the picture, and generates a prediction image corresponding to the sub-block without referring to spatial gradients of luminance.