公开(公告)号：US20240232064A1

公开(公告)日：2024-07-11

申请号：US18408355

申请日：2024-01-09

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Craig E. Hampel

IPC: G06F12/02

CPC classification number: G06F12/02 ,  G06F12/0292

Abstract: Improvements are disclosed for “leveling” or averaging out more evenly the number of activate/precharge cycles seen by the rows of a memory component, so that one or more particular rows are not excessively stressed (relative to the other rows). In one embodiment, a memory controller includes remapping facilities arranged to move data stored in a physical row from RPK to RPK′ and modify the mapping from logical row RLK while minimizing impact on normal read/write operations. Remapping operations may be scheduled relative to refresh or other maintenance operations. Remapping operations may be conditionally deferred so as to minimize performance impact.

公开(公告)号：US20230376249A1

公开(公告)日：2023-11-23

申请号：US18340810

申请日：2023-06-23

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Craig E. Hampel ,  Wayne S. Richardson ,  Chad A. Bellows ,  Lawrence Lai

IPC: G06F3/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4097 ,  G11C8/06

CPC classification number: G06F3/0659 ,  G11C7/1006 ,  G11C7/1042 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4097 ,  G11C8/06 ,  G06F3/0613 ,  G06F3/0673

Abstract: A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.

公开(公告)号：US20230350603A1

公开(公告)日：2023-11-02

申请号：US18139190

申请日：2023-04-25

Applicant: Rambus Inc.

Inventor： Taeksang Song ,  Evan Lawrence Erickson ,  Craig E. Hampel

IPC: G06F3/06

CPC classification number: G06F3/0658 ,  G06F3/0622 ,  G06F3/0679

Abstract: Technologies for securing dynamic random access memory contents to nonvolatile memory in a persistent memory module are described. One persistent memory module includes an inline memory encryption (IME) circuit that receives a data stream from a host, encrypts the data stream into encrypted data, and stores the encrypted data in DRAM. A management processor transfers the encrypted data from the DRAM to persistent storage memory responsive to a signal associated with a power-loss or power-down event.

公开(公告)号：US20230101873A1

公开(公告)日：2023-03-30

申请号：US17957201

申请日：2022-09-30

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Craig E. Hampel

IPC: G06F13/16 ,  G11C7/10 ,  G11C5/04 ,  G11C11/4096 ,  G06F13/40 ,  G11C11/408 ,  G11C11/4093

Abstract: A memory module includes a substrate, plural memory devices, and a buffer. The plural memory devices are organized into at least one rank, each memory device having plural banks. The buffer includes a primary interface for communicating with a memory controller and a secondary interface coupled to the plural memory devices. For each bank of each rank of memory devices, the buffer includes data buffer circuitry and address buffer circuitry. The data buffer circuitry includes first storage to store write data transferred during a bank cycle interval (tRR). The address buffer circuitry includes second storage to store address information corresponding to the data stored in the first storage.

公开(公告)号：US20220278759A1

公开(公告)日：2022-09-01

申请号：US17575255

申请日：2022-01-13

Applicant: Rambus Inc.

Inventor： Craig E. Hampel ,  Frederick A. Ware ,  Richard E. Perego

IPC: H04B17/11 ,  H04L7/00 ,  H04L7/04 ,  H04L7/10 ,  H04L27/00 ,  H04B17/21 ,  H04B17/00

Abstract: A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.

公开(公告)号：US20220138042A1

公开(公告)日：2022-05-05

申请号：US17481246

申请日：2021-09-21

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Craig E. Hampel

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/16 ,  H03M13/09

Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation

公开(公告)号：US10983933B2

公开(公告)日：2021-04-20

申请号：US16840341

申请日：2020-04-04

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Craig E. Hampel

IPC: G06F13/16 ,  G11C7/10 ,  G11C5/04 ,  G11C11/4096 ,  G06F13/40 ,  G11C11/408 ,  G11C11/4093

Abstract: A memory module includes a substrate, plural memory devices, and a buffer. The plural memory devices are organized into at least one rank, each memory device having plural banks. The buffer includes a primary interface for communicating with a memory controller and a secondary interface coupled to the plural memory devices. For each bank of each rank of memory devices, the buffer includes data buffer circuitry and address buffer circuitry. The data buffer circuitry includes first storage to store write data transferred during a bank cycle interval (tRR). The address buffer circuitry includes second storage to store address information corresponding to the data stored in the first storage.

公开(公告)号：US20210049115A1

公开(公告)日：2021-02-18

申请号：US17009102

申请日：2020-09-01

Applicant: Rambus Inc.

Inventor： Craig E. Hampel ,  Frederick A. Ware

IPC: G06F13/16 ,  G06F13/42 ,  G11C5/04 ,  G11C7/10 ,  H05K1/18 ,  G06F12/1081 ,  G06F13/28

Abstract: A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

公开(公告)号：US10795834B2

公开(公告)日：2020-10-06

申请号：US16223031

申请日：2018-12-17

Applicant: Rambus Inc.

Inventor： Craig E. Hampel ,  Frederick A. Ware

IPC: G06F13/16 ,  G06F13/42 ,  G11C5/04 ,  G11C7/10 ,  H05K1/18 ,  G06F12/1081 ,  G06F13/28

Abstract: A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

公开(公告)号：US10673582B2

公开(公告)日：2020-06-02

申请号：US16378084

申请日：2019-04-08

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Richard E. Perego ,  Craig E. Hampel

IPC: H04L7/00 ,  H04L1/24 ,  H04L7/10 ,  H04L25/02 ,  H04L25/12 ,  G11C29/02 ,  G11C7/10 ,  H04L27/00 ,  G11C7/04 ,  H04L7/033

Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.