公开(公告)号：US20230282266A1

公开(公告)日：2023-09-07

申请号：US18181185

申请日：2023-03-09

申请人： Rambus Inc.

发明人： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

IPC分类号： G11C11/406 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C29/02 ,  G06F1/3234 ,  G11C11/4074

CPC分类号： G11C11/40615 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C29/022 ,  G11C29/028 ,  G06F1/3234 ,  G11C11/4074

摘要： In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

公开(公告)号：US20220365552A1

公开(公告)日：2022-11-17

申请号：US17830163

申请日：2022-06-01

申请人： Rambus Inc.

发明人： Jun Kim ,  Pak Shing Chau ,  Wayne S. Richardson

IPC分类号： G06F1/08 ,  H03L7/099 ,  H04L7/00 ,  H03L7/081 ,  H03L7/07 ,  H04L7/10 ,  G06F13/16 ,  G06F1/10

摘要： A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.

公开(公告)号：US20220172760A1

公开(公告)日：2022-06-02

申请号：US17531151

申请日：2021-11-19

申请人： Rambus Inc.

发明人： Ian Shaeffer ,  Lawrence Lai ,  Fan Ho ,  David A. Secker ,  Wayne S. Richardson ,  Akash Bansal ,  Brian S. Leibowitz ,  Kyung Suk Oh

IPC分类号： G11C8/12 ,  G11C5/06 ,  G11C5/02 ,  G11C8/18 ,  H01L25/065 ,  G11C5/04 ,  G11C7/10 ,  H01L23/00

摘要： A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

公开(公告)号：US11128388B2

公开(公告)日：2021-09-21

申请号：US16582448

申请日：2019-09-25

申请人： Rambus Inc.

发明人： Jun Kim ,  Wayne S. Richardson ,  Glenn Chiu

IPC分类号： H04B17/11 ,  H04L5/14 ,  H04L25/03

摘要： A method for calibrating a communication channel coupling first and second components includes transmitting a data signal from the first component to the second component on the communication channel, and sensing a characteristic, such as phase, of the data signal on the second component. Information about the sensed characteristic is fed back to the first component using an auxiliary channel. An adjustable parameter, such as phase, for the transmitter is adjusted on the first component in response to the information. Also, a characteristic of a data signal received from the transmitter on the second component is sensed and used to adjust an adjustable parameter for the receiver on the first component.

公开(公告)号：US20170103802A1

公开(公告)日：2017-04-13

申请号：US15332785

申请日：2016-10-24

申请人： Rambus Inc.

发明人： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

IPC分类号： G11C11/406 ,  G11C11/4074

CPC分类号： G11C11/40615 ,  G06F1/3234 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C29/022 ,  G11C29/028

摘要： In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

公开(公告)号：US09568942B2

公开(公告)日：2017-02-14

申请号：US14961077

申请日：2015-12-07

申请人： Rambus Inc.

发明人： Jun Kim ,  Pak Shing Chau ,  Wayne S. Richardson

IPC分类号： G06F1/00 ,  G06F1/08 ,  H03L7/099 ,  H04L7/00 ,  H03L7/081 ,  H03L7/07 ,  H04L7/10 ,  G06F13/16 ,  G06F1/10

CPC分类号： G06F1/08 ,  G06F1/10 ,  G06F13/1673 ,  G06F13/1689 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/0995 ,  H04L7/0008 ,  H04L7/0033 ,  H04L7/10 ,  Y02D10/14

摘要： A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.

摘要翻译： 一种存储器系统，其中通过测量在具有低于第一定时的频率的第二定时信号中出现的实际相位延迟来确定在存储器件中用于数据传输的第一定时信号的分配中将发生的定时漂移 并且分布在模拟第一定时信号的分布的至少一部分的漂移特性的一个或多个电路中。 实际的相位延迟在存储器件中确定并提供给存储器控制器，使得用于数据传输的定时信号的相位可以基于所确定的定时漂移来调整。

公开(公告)号：US09502096B2

公开(公告)日：2016-11-22

申请号：US14573323

申请日：2014-12-17

申请人： Rambus Inc.

发明人： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

IPC分类号： G11C7/00 ,  G11C11/406 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C29/02 ,  G06F1/32 ,  G11C11/4074

CPC分类号： G11C11/40615 ,  G06F1/3234 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C29/022 ,  G11C29/028

摘要： In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

公开(公告)号：US09117496B2

公开(公告)日：2015-08-25

申请号：US13753360

申请日：2013-01-29

申请人： Rambus Inc.

发明人： Ian Shaeffer ,  Lawrence Lai ,  Fan Ho ,  David A. Secker ,  Wayne S. Richardson ,  Akash Bansal ,  Brian S. Leibowitz ,  Kyung Suk Oh

IPC分类号： G11C5/06 ,  G11C5/04 ,  G11C7/10 ,  H01L23/00 ,  H01L25/065

CPC分类号： G11C8/12 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/1012 ,  G11C7/1045 ,  G11C8/18 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

摘要： A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

摘要翻译： 描述了包括可编程命令和地址（CA）接口和/或可编程数据接口的存储器件。 在操作模式下，两个或多个CA接口可能处于活动状态。 在另一操作模式中，至少一个但不是全部的CA接口可能是活动的。 在操作模式下，所有数据接口都可能处于活动状态。 在另一种操作模式中，至少一个但不是全部的数据接口可能是活动的。 存储器装置可以包括用于选择：操作模式的电路; 操作模式中的子模式; 一个或多个CA接口作为活动CA接口; 来自多个活动CA接口的主CA接口; 和/或一个或多个数据接口作为活动数据接口。 电路可以基于一个或多个寄存器中的一个或多个位和/或在一个或多个引脚上接收到的一个或多个信号来执行这些选择。

公开(公告)号：US20230409072A1

公开(公告)日：2023-12-21

申请号：US18206867

申请日：2023-06-07

申请人： Rambus Inc.

发明人： Jun Kim ,  Pak Shing Chau ,  Wayne S. Richardson

IPC分类号： G06F1/08 ,  H03L7/099 ,  H04L7/00 ,  H03L7/081 ,  H03L7/07 ,  H04L7/10 ,  G06F13/16 ,  G06F1/10

CPC分类号： G06F1/08 ,  H03L7/0995 ,  H04L7/0008 ,  H03L7/0814 ,  H04L7/0033 ,  H03L7/07 ,  H04L7/10 ,  G06F13/1689 ,  G06F1/10 ,  G06F13/1673 ,  Y02D10/00

摘要： A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.

公开(公告)号：US11783879B2

公开(公告)日：2023-10-10

申请号：US17531151

申请日：2021-11-19

申请人： Rambus Inc.

发明人： Ian Shaeffer ,  Lawrence Lai ,  Fan Ho ,  David A. Secker ,  Wayne S. Richardson ,  Akash Bansal ,  Brian S. Leibowitz ,  Kyung Suk Oh

IPC分类号： G11C8/12 ,  G11C5/06 ,  G11C5/02 ,  G11C8/18 ,  H01L25/065 ,  G11C5/04 ,  G11C7/10 ,  H01L23/00

CPC分类号： G11C8/12 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/1012 ,  G11C7/1045 ,  G11C8/18 ,  H01L24/49 ,  H01L25/0657 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/48095 ,  H01L2924/00014 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/49171 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/49171 ,  H01L2224/48471 ,  H01L2924/00 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2924/00 ,  H01L2924/181 ,  H01L2924/00012

摘要： A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.