公开(公告)号：US07098043B2

公开(公告)日：2006-08-29

申请号：US10759468

申请日：2004-01-15

申请人： Wei-Wei Zhuang ,  Lisa H. Stecker ,  Gregory M. Stecker ,  Sheng Teng Hsu

发明人： Wei-Wei Zhuang ,  Lisa H. Stecker ,  Gregory M. Stecker ,  Sheng Teng Hsu

IPC分类号： H01L21/00

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1683

摘要： A Pr1-XCaXMnO3 (PCMO) spin-coat deposition method for eliminating voids is provided, along with a void-free PCMO film structure. The method comprises: forming a substrate, including a noble metal, with a surface; forming a feature, such as a via or trench, normal with respect to the substrate surface; spin-coating the substrate with acetic acid; spin-coating the substrate with a first, low concentration of PCMO solution; spin-coating the substrate with a second concentration of PCMO solution, having a greater concentration of PCMO than the first concentration; baking and RTA annealing (repeated one to five times); post-annealing; and, forming a PCMO film with a void-free interface between the PCMO film and the underlying substrate surface. The first concentration of PCMO solution has a PCMO concentration in the range of 0.01 to 0.1 moles (M). The second concentration of PCMO solution has a PCMO concentration in the range of 0.2 to 0.5 M.

摘要翻译： 提供了一种用于消除空隙的Pr 1-X C 3 Mn 3 O 3（PCMO）旋涂沉积方法，以及无空隙 PCMO薄膜结构。 该方法包括：用表面形成包括贵金属的基底; 形成相对于衬底表面正常的特征，例如通孔或沟槽; 用乙酸旋涂底物; 用第一种低浓度的PCMO溶液旋涂底物; 以第二浓度的PCMO溶液旋涂底物，其具有比第一浓度更高浓度的PCMO; 烘烤和RTA退火（重复1〜5次）; 后退火; 并且在PCMO膜和下面的衬底表面之间形成具有无空隙界面的PCMO膜。 PCMO溶液的第一浓度的PCMO浓度范围为0.01至0.1摩尔（M）。 PCMO溶液的第二浓度的PCMO浓度范围为0.2-0.5M。

公开(公告)号：US07094691B2

公开(公告)日：2006-08-22

申请号：US10410029

申请日：2003-04-09

申请人： Wei Pan ,  Robert Barrowcliff ,  David R. Evans ,  Sheng Teng Hsu

发明人： Wei Pan ,  Robert Barrowcliff ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： H01L21/44

CPC分类号： H01L21/76841 ,  C23C16/34

摘要： A method of forming a tungsten nitride thin film in an integrated circuit includes preparing a silicon substrate on a silicon wafer and placing the silicon wafer in a heatable chuck in a CVD vacuum chamber; placing a known quantity of a tungsten source in a variable-temperature bubbler to provide a gaseous tungsten source; setting the variable-temperature bubbler to a predetermined temperature; passing a carrier gas through the variable-temperature bubbler and carrying the gaseous tungsten source with the carrier gas into the CVD vacuum chamber; introducing a nitrogen-containing reactant gas into the CVD vacuum chamber; reacting the gaseous tungsten source and the nitrogen-containing reactant gas above the surface of the silicon wafer in a deposition process to deposit a WxNy thin film on the surface of the silicon wafer; and completing the integrated circuit containing the WxNy thin film.

摘要翻译： 在集成电路中形成氮化钨薄膜的方法包括在硅晶片上制备硅衬底，并将硅晶片放置在CVD真空室中的可加热卡盘中; 将已知量的钨源放置在可变温度起泡器中以提供气态钨源; 将可变温度起泡器设定到预定温度; 使载气通过可变温度起泡器并将载气的气态钨源运送到CVD真空室中; 将含氮反应气体引入CVD真空室中; 在沉积过程中使气态钨源和硅晶片表面上方的含氮反应物气体反应，以沉积W 1 / N 2 N 2 O 3 硅晶片; 并完成包含W＆lt; N＆gt; N＆gt; Y＆lt;＆lt;＆lt;＆lt;薄膜的集成电路。

公开(公告)号：US07060586B2

公开(公告)日：2006-06-13

申请号：US10836689

申请日：2004-04-30

申请人： Tingkai Li ,  Wei-Wei Zhuang ,  David R. Evans ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Wei-Wei Zhuang ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： H01L21/20 ,  H01L29/00

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： PrCaMnO (PCMO) thin films with predetermined memory-resistance characteristics and associated formation processes have been provided. In one aspect the method comprises: forming a Pr3+1−xCa2+xMnO thin film composition, where 0.1

摘要翻译： 已经提供了具有预定的记忆电阻特性和相关的形成过程的PrCaMnO（PCMO）薄膜。 在一个方面，所述方法包括：形成Pr 3+ 1-x 2 Ca 2 O 3 x MnO薄膜 组成，其中0.1 _0.78Mn^{4+<​​/SUP>_0.22O2-_{2.96 组合， Mn和O离子的比例变化如下：O 2 - （2.96）; Mn（3+）+（（1-x）+ 8％）; 和Mn 4+（x-8％）。 在另一方面，该方法响应于晶体取向在PCMO膜中产生密度。 例如，如果PCMO膜具有（110）取向，则在垂直于（110）取向的平面中产生在每平方英尺5至6.76个Mn原子的范围内的密度。}}

公开(公告)号：US07053403B1

公开(公告)日：2006-05-30

申请号：US11339876

申请日：2006-01-26

申请人： Fengyan Zhang ,  Gregory M. Stecker ,  Robert A. Barrowcliff ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Gregory M. Stecker ,  Robert A. Barrowcliff ,  Sheng Teng Hsu

IPC分类号： H01L29/10 ,  H01L29/12

CPC分类号： H01L21/31111 ,  B81C1/00111 ,  B82Y10/00

摘要： A method is provided for patterning iridium oxide (IrOx) nanostructures. The method comprises: forming a substrate first region adjacent a second region; growing IrOx nanostructures from a continuous IrOx film overlying the first region; simultaneously growing IrOx nanostructures from a non-continuous IrOx film overlying the second region; selectively etching areas of the second region exposed by the non-continuous IrOx film; and, lifting off the IrOx nanostructures overlying the second region. Typically, the first region is formed from a first material and the second region from a second material, different than the first material. For example, the first material can be a refractory metal, or refractory metal oxide. The second material can be SiOx. The step of selectively etching areas of the second region exposed by the non-continuous IrOx film includes exposing the substrate to an etchant that is more reactive with the second material than the IrOx.

摘要翻译： 提供了用于构图氧化铱（IrOx）纳米结构的方法。 该方法包括：在第二区域附近形成衬底第一区域; 从覆盖第一区域的连续IrOx膜生长IrOx纳米结构; 同时从覆盖第二区域的非连续IrOx膜生长IrOx纳米结构; 选择性地蚀刻由非连续IrOx膜暴露的第二区域的区域; 并提升覆盖第二区域的IrOx纳米结构。 通常，第一区域由第一材料形成，第二区域由不同于第一材料的第二材料形成。 例如，第一种材料可以是难熔金属或难熔金属氧化物。 第二种材料可以是SiOx。 选择性地蚀刻由非连续IrOx膜暴露的第二区域的区域的步骤包括将衬底暴露于与IrOx比第二材料更具反应性的蚀刻剂。

公开(公告)号：US07022621B1

公开(公告)日：2006-04-04

申请号：US11013804

申请日：2004-12-15

申请人： Fengyan Zhang ,  Gregory M. Stecker ,  Robert A. Barrowcliff ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Gregory M. Stecker ,  Robert A. Barrowcliff ,  Sheng Teng Hsu

IPC分类号： H01L21/461

CPC分类号： H01L21/31111 ,  B81C1/00111 ,  B82Y10/00

摘要： A method is provided for patterning iridium oxide (IrOx) nanostructures. The method comprises: forming a substrate first region adjacent a second region; growing IrOx nanostructures from a continuous IrOx film overlying the first region; simultaneously growing IrOx nanostructures from a non-continuous IrOx film overlying the second region; selectively etching areas of the second region exposed by the non-continuous IrOx film; and, lifting off the IrOx nanostructures overlying the second region. Typically, the first region is formed from a first material and the second region from a second material, different than the first material. For example, the first material can be a refractory metal, or refractory metal oxide. The second material can be SiOx. The step of selectively etching areas of the second region exposed by the non-continuous IrOx film includes exposing the substrate to an etchant that is more reactive with the second material than the IrOx.

摘要翻译： 提供了用于构图氧化铱（IrOx）纳米结构的方法。 该方法包括：在第二区域附近形成衬底第一区域; 从覆盖第一区域的连续IrOx膜生长IrOx纳米结构; 同时从覆盖第二区域的非连续IrOx膜生长IrOx纳米结构; 选择性地蚀刻由非连续IrOx膜暴露的第二区域的区域; 并提升覆盖第二区域的IrOx纳米结构。 通常，第一区域由第一材料形成，第二区域由不同于第一材料的第二材料形成。 例如，第一种材料可以是难熔金属或难熔金属氧化物。 第二种材料可以是SiOx。 选择性地蚀刻由非连续IrOx膜暴露的第二区域的区域的步骤包括将衬底暴露于与IrOx比第二材料更具反应性的蚀刻剂。

公开(公告)号：US07015147B2

公开(公告)日：2006-03-21

申请号：US10625065

申请日：2003-07-22

申请人： Jong-Jan Lee ,  Sheng Teng Hsu

发明人： Jong-Jan Lee ,  Sheng Teng Hsu

IPC分类号： H01L21/302

CPC分类号： H01L29/66772 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78639 ,  H01L29/78654

摘要： A method for fabrication of silicon-on-nothing (SON) MOSFET using selective etching of Si1−xGex layer, includes preparing a silicon substrate; growing an epitaxial Si1−xGex layer on the silicon substrate; growing an epitaxial thin top silicon layer on the epitaxial Si1−xGex layer; trench etching of the top silicon and Si1−xGex, into the silicon substrate to form a first trench; selectively etching the Si1−xGex layer to remove substantially all of the Si1−xGex to form an air gap; depositing a layer of SiO2 by CVD to fill the first trench; trench etching to from a second trench; selectively etching the remaining Si1−xGex layer; depositing a second layer of SiO2 by CVD to fill the second trench, thereby decoupling a source, a drain and a channel from the substrate; and completing the structure by state-of-the-art CMOS fabrication techniques.

摘要翻译： 使用Si 1-x Ge层的选择性蚀刻制造无硅无硅（SON）MOSFET的方法包括制备硅衬底; 在硅衬底上生长外延Si 1-x Ge层x层; 在外延Si 1-x Ge层上生长外延薄顶硅层; 将硅和Si 1-x N x X x x沟槽蚀刻到硅衬底中以形成第一沟槽; 选择性地蚀刻Si 1-x Ge Ge层，以便基本上除去所有的Si 1-x N x Ge x Si 形成气隙; 通过CVD沉积SiO 2层以填充第一沟槽; 从第二沟槽进行沟槽蚀刻; 选择性地蚀刻剩余的Si 1-x N Ge x层; 通过CVD沉积SiO 2的第二层以填充第二沟槽，从而使源极，漏极和沟道与衬底去耦合; 并通过最先进的CMOS制造技术完成结构。

公开(公告)号：US06911361B2

公开(公告)日：2005-06-28

申请号：US10384846

申请日：2003-03-10

申请人： Fengyan Zhang ,  Wei-Wei Zhuang ,  Wei Pan ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Wei-Wei Zhuang ,  Wei Pan ,  Sheng Teng Hsu

IPC分类号： H01L27/108 ,  G11C13/00 ,  H01L45/00 ,  H01L21/8242 ,  H01L21/31 ,  H01L21/469

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/147 ,  H01L45/1608

摘要： A method of applying a PCMO thin film on an iridium substrate for use in a RRAM device, includes preparing a substrate; depositing a barrier layer on the substrate; depositing a layer of iridium on the barrier layer; spin coating a layer of PCMO on the iridium; baking the PCMO and substrate in a three-step baking process; post-bake annealing the substrate and the PCMO in a RTP chamber; repeating said spin coating, baking and annealing steps until the PCMO has a desired thickness; annealing the substrate and PCMO; depositing a top electrode; and completing the RRAM device.

摘要翻译： 在用于RRAM器件的铱衬底上施加PCMO薄膜的方法包括制备衬底; 在衬底上沉积阻挡层; 在阻挡层上沉积一层铱; 在铱上旋涂一层PCMO; 在三步烘烤过程中烘烤PCMO和基材; 在RTP室中对基板和PCMO进行后烘烤退火; 重复所述旋涂，烘烤和退火步骤直到PCMO具有所需的厚度; 退火基板和PCMO; 沉积顶部电极; 并完成RRAM设备。

公开(公告)号：US06899858B2

公开(公告)日：2005-05-31

申请号：US10350641

申请日：2003-01-23

申请人： Wei-Wei Zhuang ,  David R. Evans ,  Sheng Teng Hsu

发明人： Wei-Wei Zhuang ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： C01G27/00 ,  C01G27/02 ,  C23C16/40 ,  H01L21/316 ,  C01B21/48

CPC分类号： C01G27/00 ,  C01G27/02

摘要： A method of preparing a hafnium nitrate thin film includes placing phosphorus pentoxide in a first vessel; connecting the first vessel to a second vessel containing hafnium tetrachloride; cooling the second vessel with liquid nitrogen; dropping fuming nitric acid into the first vessel producing N2O5 gas; allowing the N2O5 gas to enter the second vessel; heating the first vessel until the reaction is substantially complete; disconnecting the two vessels; removing the second vessel from the liquid nitrogen bath; heating the second vessel; refluxing the contents of the second vessel; drying the compound in the second vessel by dynamic pumping; purifying the compound in the second vessel by sublimation to form Hf(NO3)4, and heating the Hf(NO3)4 to produce HfO2 for use in an ALCVD process.

摘要翻译： 制备硝酸铪薄膜的方法包括将五氧化二磷放置在第一容器中; 将第一容器连接到含有四氯化铪的第二容器; 用液氮冷却第二个容器; 将发烟硝酸滴入产生N 2 O 5气体的第一容器中; 允许N 2 O 5气体进入第二容器; 加热第一个容器直到反应基本完成; 断开两艘船舶; 从液氮浴中除去第二容器; 加热第二艘船; 回流第二容器的内容物; 通过动态泵送干燥第二容器中的化合物; 通过升华纯化第二容器中的化合物以形成Hf（NO 3 N 3）4，并加热Hf（NO 3 N 3）3 4生产用于ALCVD工艺的HfO 2 2。

公开(公告)号：US06897530B2

公开(公告)日：2005-05-24

申请号：US10261447

申请日：2002-09-30

申请人： Sheng Teng Hsu

发明人： Sheng Teng Hsu

IPC分类号： H01L29/786 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： A transistor structure includes a main gate silicon active region having a thickness of less than or equal to 30 nm; and auxiliary gate active regions located on either side of said main gate silicon active region, said auxiliary gate active regions being spaced a distance from said main gate active region of about 200 nm. A method of forming an ultra-thin SOI MOS transistor includes preparing a silicon wafer, including forming a top silicon layer having a thickness of between about 100 nm to 200 nm, thinning the top silicon layer to a thickness of between about 10 nm to 30 nm, and forming an oxide layer over the top silicon layer; forming a layer of material taken from the group of material consisting of polysilicon and silicide; forming an oxide cap on the formed layer of material, and etching the oxide cap and layer of material to form a main gate electrode and an auxiliary gate electrode on either side thereof; forming an oxide layer over the structure and etching the oxide layer to form sidewall oxide structures about the gate electrodes; depositing a layer of material taken from the group of material consisting of polysilicon, silicide and metal, etching the newly deposited layer of material, and metallizing the structure.

摘要翻译： 晶体管结构包括厚度小于或等于30nm的主栅极硅有源区; 以及位于所述主栅极硅有源区两侧的辅助栅极有源区，所述辅助栅极有源区与所述主栅极有源区间隔开约200nm的距离。 形成超薄SOI MOS晶体管的方法包括制备硅晶片，其包括形成厚度在约100nm至200nm之间的顶部硅层，将顶部硅层变薄至约10nm至30nm的厚度 并且在顶部硅层上形成氧化物层; 形成从由多晶硅和硅化物组成的材料组中取出的材料层; 在所形成的材料层上形成氧化物盖，蚀刻氧化物盖和材料层，以在其两侧形成主栅电极和辅助栅电极; 在所述结构上形成氧化物层并蚀刻所述氧化物层以形成围绕所述栅电极的侧壁氧化物结构; 沉积从由多晶硅，硅化物和金属组成的材料组中取出的材料层，蚀刻新沉积的材料层，并对结构进行金属化。

公开(公告)号：US06897074B1

公开(公告)日：2005-05-24

申请号：US10794736

申请日：2004-03-03

申请人： Fengyan Zhang ,  Wei-Wei Zhuang ,  Jong-Jan Lee ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Wei-Wei Zhuang ,  Jong-Jan Lee ,  Sheng Teng Hsu

IPC分类号： H01L21/00 ,  H01L21/02 ,  H01L21/316 ,  H01L41/22

CPC分类号： H01L21/31691 ,  H01L28/55 ,  H01L41/317

摘要： A method for forming a doped PGO ferroelectric thin film, and related doped PGO thin film structures are described. The method comprising: forming either an electrically conductive or electrically insulating substrate; forming a doped PGO film overlying the substrate; annealing; crystallizing; and, forming a single-phase c-axis doped PGO thin film overlying the substrate, having a Curie temperature of greater than 200 degrees C. Forming a doped PGO film overlying the substrate includes depositing a doped precursor in the range between 0.1N and 0.5N, with a molecular formula of Pby-xMxGe3O11, where: M is a doping element; y=4.5 to 6; and, x=0.1 to 1. The element M can be Sn, Ba, Sr, Cd, Ca, Pr, Ho, La, Sb, Zr, or Sm.

摘要翻译： 描述了用于形成掺杂的PGO铁电薄膜的方法以及相关的掺杂PGO薄膜结构。 该方法包括：形成导电或电绝缘的衬底; 在衬底上形成掺杂的PGO膜; 退火; 结晶 并且形成覆盖在衬底上的单相c轴掺杂的PGO薄膜，其居里温度大于200℃。形成覆盖在衬底上的掺杂PGO膜包括沉积在0.1N和0.5之间的掺杂前体 N，具有分子式为Pb x Si x N x N x O 11，其中：M是掺杂物 元件; y = 4.5〜6; x = 0.1〜1。元素M可以是Sn，Ba，Sr，Cd，Ca，Pr，Ho，La，Sb，Zr或Sm。