公开(公告)号：US20050237682A1

公开(公告)日：2005-10-27

申请号：US10831897

申请日：2004-04-26

申请人： Yi-Hsun Wu ,  Jian-Hsing Lee

发明人： Yi-Hsun Wu ,  Jian-Hsing Lee

IPC分类号： H01L27/02 ,  H02H9/00

CPC分类号： H01L27/0266

摘要： A circuit and a method for solving the general problem of protecting core devices in integrated circuits from electrostatic discharge damage is provided. This circuit and a method prevents ESD voltage breakdown of thin oxide field effect transistors which are directly connected to the core Vdd power supply. The embodiments of this invention use inverter buffers using a thick or thin oxide devices at the input to the core circuitry is to be protected. Other embodiments of this invention use pass transistor or transfer gates made with thick or thin oxide devices at the input to the core circuitry is to be protected.

摘要翻译： 提供了解决集成电路中的核心器件保护静电放电损坏的一般问题的电路和方法。 该电路和方法防止直接连接到核心Vdd电源的薄氧化物场效应晶体管的ESD电压击穿。 使用在核心电路的输入端使用厚或薄的氧化物装置的逆变器缓冲器的保护。 本发明的其它实施例使用传输晶体管或由厚或薄的氧化物器件制成的传输栅极在核心电路的输入端被保护。

公开(公告)号：US06803259B2

公开(公告)日：2004-10-12

申请号：US10404620

申请日：2003-03-31

申请人： Jian-Hsing Lee

发明人： Jian-Hsing Lee

IPC分类号： H01L21332

CPC分类号： H01L27/0262 ,  H01L29/74

摘要： A silicon controlled rectifier for SiGe process. The silicon controlled rectifier comprises a substrate, a buried layer of a first conductivity type in the substrate, a well of the first conductivity type in the substrate and above the buried layer, a doped region of a second conductivity type in the well, a first conducting layer of the second conductivity type on the substrate, and a second conducting layer of the first conductivity type on the first conducting layer.

公开(公告)号：US06784498B1

公开(公告)日：2004-08-31

申请号：US10403976

申请日：2003-03-31

申请人： Jian-Hsing Lee ,  Yi-Hsun Wu

发明人： Jian-Hsing Lee ,  Yi-Hsun Wu

IPC分类号： H01L2362

CPC分类号： H01L27/0262 ,  H01L29/0692 ,  H01L29/87

摘要： A low capacitance ESD protection device. The device comprises a substrate, a well of a first conductivity type in the substrate, a first and second transistor of the first conductivity type respectively on two sides of the well, a guard ring of a second conductivity type in the substrate, surrounding the well, and the first and second transistor, and a doped region of the second conductivity type in the well, wherein profiles of a drain and source region of each of the first and second transistor are un-symmetrical.

摘要翻译： 低电容ESD保护器件。 该器件包括衬底，衬底中的第一导电类型的阱，分别在阱的两侧上的第一导电类型的第一和第二晶体管，衬底中的第二导电类型的保护环，围绕阱 以及第一和第二晶体管，以及阱中的第二导电类型的掺杂区域，其中第一和第二晶体管中的每一个的漏极和源极区域的剖面是不对称的。

公开(公告)号：US06703663B1

公开(公告)日：2004-03-09

申请号：US09655086

申请日：2000-09-05

申请人： Jian-Hsing Lee ,  Yi-Hsun Wu ,  Jian-Ren Shih

发明人： Jian-Hsing Lee ,  Yi-Hsun Wu ,  Jian-Ren Shih

IPC分类号： H01L2976

CPC分类号： H01L29/7833 ,  H01L21/823814 ,  H01L27/0266 ,  H01L29/1083

摘要： A method of forming a semiconductor memory device formed on a semiconductor substrate with an N-well and a P-well comprises the following steps. Form over a substrate the combination of a gate oxide layer and a gate layer patterned into gate stacks with sidewalls for an NMOS FET device over a P-well in the substrate and a PMOS FET device over an N-well. Form P− lightly doped S/D regions in the N-well and N− lightly doped S/D regions in the P-well. Form spacers on the sidewalls of the gate stacks. Thereafter form deep N− lightly doped S/D regions in the P-well, and form deep P− lightly doped S/D regions in the N-well. Form heavily doped P++ regions self-aligned with the gate below future P+ S/D sites to be formed self-aligned with the spacers in the N-well, and form heavily doped N++ regions self-aligned with the gate below future N+ S/D sites to be formed self-aligned with the spacers in the P-well.

摘要翻译： 用N阱和P阱形成在半导体衬底上的半导体存储器件的形成方法包括以下步骤。 在衬底上形成栅极氧化物层和栅极层的组合，栅极层与衬底中的P阱上的NMOS FET器件的侧壁和N阱上的PMOS FET器件构图成栅极堆叠。 在P阱中的N阱和N-轻掺杂的S / D区中形成P-轻掺杂的S / D区。 在栅极堆叠的侧壁上形成间隔物。 然后在P阱中形成深N轻掺杂的S / D区，并在N阱中形成深P-轻掺杂的S / D区。 形成与未来P + S / D位置下方的栅极自对准的重掺杂P ++区域，以与N阱中的间隔物自对准，并形成与未来N + S / D的栅极自对准的重掺杂N ++区域， D点与P阱中的间隔物自对准。

公开(公告)号：US06682993B1

公开(公告)日：2004-01-27

申请号：US10161007

申请日：2002-05-31

申请人： Yi-Hsun Wu ,  Jian-Hsing Lee

发明人： Yi-Hsun Wu ,  Jian-Hsing Lee

IPC分类号： H01L2104

CPC分类号： H01L27/0266

摘要： The invention consists of an ESD protection discharging NMOS with a special drain dopant region that enables a lower voltage trigger point for Vcc to Vss ESD power protection. To enable this ESD protection, the NMOS source connected to a first voltage bus line, or Vcc, and the drain is connected to a second voltage bus line, or ground. The NMOS device gate is connected to ground through a difflused resistor assuring the device remains in an off state during normal operation. The unique invention special dopant region is located under and around the NMOS drain which lowers the drain to substrate breakdown voltage enabling the ESD protection current discharge to start at a lower voltage than otherwise. This feature reduces voltage stress on the gates of active devices being protected, and enables higher ESD current discharges at the same power level as for devices without the special drain dopant region.

摘要翻译： 本发明包括具有特殊漏极掺杂剂区域的ESD保护放电NMOS，其能够实现用于Vcc至Vss ESD功率保护的较低电压触发点。 为了实现该ESD保护，连接到第一电压总线或Vcc的NMOS源和漏极连接到第二电压总线或地。 NMOS器件栅极通过差分电阻器连接到地，确保器件在正常工作期间保持关断状态。 独特的发明特殊掺杂剂区域位于NMOS漏极的下面和周围，这降低了漏极到衬底的击穿电压，使得ESD保护电流放电能够以比其他电压更低的电压开始。 该特性降低了受保护的有源器件的栅极上的电压应力，并且能够实现与没有特殊漏极掺杂剂区域的器件相同功率电平的更高的ESD电流放电。

公开(公告)号：US06492208B1

公开(公告)日：2002-12-10

申请号：US09671214

申请日：2000-09-28

申请人： Tao Cheng ,  Jian-Hsing Lee

发明人： Tao Cheng ,  Jian-Hsing Lee

IPC分类号： H01L21332

CPC分类号： H01L27/0262

摘要： An embedded parasitic silicon controlled rectifier (SCR) in conjunction with a Gated-NMOS is created for protecting a chip input or output pad from electrostatic discharge ESD, by inserting a p+ diffusion and the n-well in the drain side and a part of the drain to forms a low-trigger, high efficiency SCR. The device layout is such that the drain connection is tightly tied together at the p+ diffusion and the n+ drain making that connection very short and, thereby, preventing latch-up. The parasitic SCR is contained entirely within the n+ diffusion (the source of the grounded gate NMOS transistor) at either side of the structure and, therefore, called an embedded SCR. For a 12 volt I/O device each of two n+ drains is placed in its own n-type doped drain (ndd) area straddling halfway the n-well. The structure is repeated as required and a p+ diffusion is implanted at both perimeters and connected to the nearest n+ source and a reference voltage.

摘要翻译： 通过在漏极侧插入p +扩散和n阱，创建了一个与门极NMOS相结合的嵌入式寄生可控硅整流器（SCR），用于保护芯片输入或输出焊盘免受静电放电ESD的影响。 漏极形成低触发，高效SCR。 器件布局使得漏极连接在p +扩散和n +漏极紧密连接在一起，使得该连接非常短，从而防止闩锁。 寄生SCR完全包含在结构两侧的n +扩散（接地栅极NMOS晶体管的源极）内，因此被称为嵌入式SCR。 对于12伏I / O设备，两个n +漏极中的每一个都放置在跨越n-阱一半的其自身的n型掺杂漏极（ndd）区域中。 根据需要重复该结构，并且在两个周边注入p +扩散并连接到最近的n +源和参考电压。

公开(公告)号：US06246075B1

公开(公告)日：2001-06-12

申请号：US09507883

申请日：2000-02-22

申请人： Hung-Der Su ,  Jian-Hsing Lee ,  Di-Son Kuo

发明人： Hung-Der Su ,  Jian-Hsing Lee ,  Di-Son Kuo

IPC分类号： H01L2358

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ensemble of test structures comprising arrays of polysilicon plate MOS capacitors for the measurement of electrical quality of the MOSFET gate insulation is described. The test structures also measure plasma damage to these gate insulators incurred during metal etching and plasma ashing of photoresist. The structures are formed, either on test wafers or in designated areas of wafers containing integrated circuit chips. One of the test structures is designed primarily to minimize plasma damage so that oxide quality, and defect densities may be measured unhampered by interface traps created by plasma exposure. Other structures provide different antenna-to-oxide area ratios, useful for assessing plasma induced oxide damage and breakdown. The current-voltage characteristics of the MOS capacitors are measured by probing the structures on the wafer, thereby providing timely process monitoring capability.

摘要翻译： 描述了包括用于测量MOSFET栅极绝缘的电气质量的多晶硅板MOS电容器阵列的测试结构的集合。 测试结构还测量在金属蚀刻和光致抗蚀剂的等离子体灰化期间引起的这些栅绝缘体的等离子体损伤。 在测试晶片上或在包含集成电路芯片的晶片的指定区域中形成结构。 其中一个测试结构主要设计为最小化等离子体损伤，从而可以通过等离子体曝光产生的界面陷阱来测量氧化物质量和缺陷密度。 其他结构提供不同的天线到氧化物面积比，可用于评估等离子体诱导的氧化物损伤和击穿。 通过探测晶片上的结构来测量MOS电容器的电流 - 电压特性，从而提供及时的过程监控能力。

公开(公告)号：US6066879A

公开(公告)日：2000-05-23

申请号：US304304

申请日：1999-05-03

申请人： Jian-Hsing Lee ,  Kuo-Chio Liu

发明人： Jian-Hsing Lee ,  Kuo-Chio Liu

IPC分类号： H01L27/02 ,  H01L23/62

CPC分类号： H01L27/0262 ,  H01L27/0266 ,  H01L29/87 ,  H01L2924/0002

摘要： A device layout is disclosed for an ESD device for protecting NMOS or Drain-Extended (DENMOS) high power transistors where the protection device (an SCR) and the NMOS or DENMOS transistors are integrated saving on silicon real estate. The integration is made possible by adding a p.sup.+ diffusion to the n-well (drain) of a high power NMOS (DENMOS) transistor such that the added p.sup.+ diffusion together with the aforementioned n-well and the p-substrate of the silicon wafer create one of the two transistors of the SCR. A low triggering voltage of the SCR is achieved by having the second parasitic npn transistor of the SCR in parallel with the NMOS (DENMOS) transistor by sharing the n-well (collector/drain), p-substrate (base/channel region), and an adjacent n.sup.+ diffusion (emitter/source) in the p-substrate. A high HBM ESD Passing Voltage is obtained by utilizing the tank oxide method of a DENMOS transistor.

摘要翻译： 公开了一种用于ESD器件的器件布局，用于保护NMOS或漏极扩展（DENMOS）高功率晶体管，其中保护器件（SCR）和NMOS或DENMOS晶体管集成在一起，可以节省硅的空间。 通过向高功率NMOS（DENMOS）晶体管的n阱（漏极）添加p +扩散使得加入的p +扩散与上述n阱和硅晶片的p-衬底一起形成，可以实现积分 SCR的两个晶体管之一。 SCR的低触发电压通过使SCR的第二寄生npn晶体管与NMOS（DENMOS）晶体管并联，通过共享n阱（集电极/漏极），p-衬底（基极/沟道区）， 和p-基底中相邻的n +扩散（发射极/源极）。 通过使用DENMOS晶体管的罐式氧化法获得高HBM ESD通过电压。

公开(公告)号：US6049484A

公开(公告)日：2000-04-11

申请号：US150907

申请日：1998-09-10

申请人： Jian-Hsing Lee ,  Kuo-Reay Peng ,  Juang-Ke Yeh ,  Ming-Chou Ho

发明人： Jian-Hsing Lee ,  Kuo-Reay Peng ,  Juang-Ke Yeh ,  Ming-Chou Ho

IPC分类号： G11C16/14 ,  G11C16/04

CPC分类号： G11C16/14

摘要： A method to erase data from a flash EEPROM is disclosed. Electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by erasing the flash EEPROM cell by first applying a high positive voltage pulse to the source of the EEPROM cell. Simultaneously, a ground reference potential is applied to the semiconductor substrate and the control gate. At this same time the drain is floating. Floating the source and drain and applying the ground reference potential to the semiconductor substrate then detraps the flash EEPROM cell. At the same time, a relatively large negative voltage pulse is applied to the control gate.

摘要翻译： 公开了一种从闪存EEPROM擦除数据的方法。 消除了捕获在闪速EEPROM的隧穿氧化物中的电荷，以在扩展编程和擦除周期之后保持编程的阈值电压和擦除的阈值电压的适当分离。 通过首先向EEPROM单元的源施加高正电压脉冲，擦除快闪EEPROM单元开始擦除快闪EEPROM单元的方法。 同时，对半导体衬底和控制栅极施加接地参考电位。 在同一时间，排水沟漂浮。 将源极和漏极浮置并将接地参考电位施加到半导体衬底，然后去除快闪EEPROM单元。 同时，向控制栅极施加相对较大的负电压脉冲。

公开(公告)号：US5726933A

公开(公告)日：1998-03-10

申请号：US857162

申请日：1997-05-15

申请人： Jian-Hsing Lee ,  Kuo-Reay Peng ,  Juang-Ke Yeh ,  Ming-Chou Ho

发明人： Jian-Hsing Lee ,  Kuo-Reay Peng ,  Juang-Ke Yeh ,  Ming-Chou Ho

IPC分类号： G11C16/10 ,  G11C16/14 ,  G11C16/06

CPC分类号： G11C16/14 ,  G11C16/10

摘要： The present invention provides method to erase and program flash EEPROMS devices using a clipped sine waveform (Vg). The clipped sine waveform reduces the tunneling oxide electric field between the floating gate and the source or drain region thereby reducing electron trapping. The method for the erase cycle comprises: applying a positive voltage to a source region; grounding a well region; floating the drain region; and simultaneously applying a negative clipped sine waveform voltage to a control gate during the erase cycle. The program cycle of the invention comprises: applying a voltage to a drain region; grounding a well region; floating a source region; and simultaneously applying a clipped sine waveform voltage to the control gate whereby the clipped sine waveforms reduce the electric field in a tunnel oxide layer which reduces the electron trapping.

摘要翻译： 本发明提供了使用限幅正弦波形（Vg）擦除和编程闪存EEPROMS设备的方法。 限幅正弦波形减少了浮动栅极和源极或漏极区域之间的隧道氧化物电场，从而减少了电子俘获。 擦除周期的方法包括：向源极区域施加正电压; 接地井区; 漂浮漏极区; 并且在擦除周期期间同时向控制栅极施加负的限幅正弦波形电压。 本发明的程序循环包括：向漏区施加电压; 接地井区; 浮动源区; 并且同时向限制栅极施加限幅正弦波形电压，由此限幅正弦波形减少隧道氧化物层中的电场，从而减少电子捕获。