公开(公告)号：US06358781B1

公开(公告)日：2002-03-19

申请号：US09607043

申请日：2000-06-30

Applicant: Jian-Hsing Lee ,  Kuo-Chio Liu ,  Bing-Lung Liao ,  Jiaw-Ren Shih

Inventor： Jian-Hsing Lee ,  Kuo-Chio Liu ,  Bing-Lung Liao ,  Jiaw-Ren Shih

IPC: H01L21332

CPC classification number: H01L27/0266

Abstract: NMOS transistors for a high voltage process are protected from electrostatic discharge (ESD) by parasitic SCRs, where the two NMOS transistors and the two SCRs are designed to be in a completely symmetrical arrangement so that the currents in the components of the SCRs are completely uniform. This symmetry is achieved by adding a p+ diffusion to the source of one of the NMOS transistors. The added p+ diffusion guarantees that the resistance seen by both SCRs is identical. This insures even current distribution between both SCRs and thereby improves the high voltage characteristics of the ESD device.

公开(公告)号：US06459127B1

公开(公告)日：2002-10-01

申请号：US10043793

申请日：2002-01-14

Applicant: Jian-Hsing Lee ,  Kuo-Chio Liu ,  Bing-Lung Liao ,  Jiaw-Ren Shih

Inventor： Jian-Hsing Lee ,  Kuo-Chio Liu ,  Bing-Lung Liao ,  Jiaw-Ren Shih

IPC: H01L2362

CPC classification number: H01L27/0266

Abstract: NMOS transistors for a high voltage process are protected from electrostatic discharge (ESD) by parasitic SCRs, where the two NMOS transistors and the two SCRs are designed to be in a completely symmetrical arrangement so that the currents in the components of the SCRs are completely uniform. This symmetry is achieved by adding a p+ diffusion to the source of one of the NMOS transistors. The added p+ diffusion guarantees that the resistance seen by both SCRs is identical. This insures even current distribution between both SCRs and thereby improves the high voltage characteristics of the ESD device.

Abstract translation: 用于高电压工艺的NMOS晶体管通过寄生SCR防止静电放电（ESD），其中两个NMOS晶体管和两个SCR被设计为完全对称的布置，使得SCR的部件中的电流是完全均匀的 。 该对称性是通过向NMOS晶体管之一的源极添加p +扩散来实现的。 添加的p +扩散保证两个SCR看到的电阻是相同的。 这确保了两个SCR之间的均匀电流分布，从而改善了ESD器件的高电压特性。

公开(公告)号：US6066879A

公开(公告)日：2000-05-23

申请号：US304304

申请日：1999-05-03

Applicant: Jian-Hsing Lee ,  Kuo-Chio Liu

Inventor： Jian-Hsing Lee ,  Kuo-Chio Liu

IPC: H01L27/02 ,  H01L23/62

CPC classification number: H01L27/0262 ,  H01L27/0266 ,  H01L29/87 ,  H01L2924/0002

Abstract: A device layout is disclosed for an ESD device for protecting NMOS or Drain-Extended (DENMOS) high power transistors where the protection device (an SCR) and the NMOS or DENMOS transistors are integrated saving on silicon real estate. The integration is made possible by adding a p.sup.+ diffusion to the n-well (drain) of a high power NMOS (DENMOS) transistor such that the added p.sup.+ diffusion together with the aforementioned n-well and the p-substrate of the silicon wafer create one of the two transistors of the SCR. A low triggering voltage of the SCR is achieved by having the second parasitic npn transistor of the SCR in parallel with the NMOS (DENMOS) transistor by sharing the n-well (collector/drain), p-substrate (base/channel region), and an adjacent n.sup.+ diffusion (emitter/source) in the p-substrate. A high HBM ESD Passing Voltage is obtained by utilizing the tank oxide method of a DENMOS transistor.

Abstract translation: 公开了一种用于ESD器件的器件布局，用于保护NMOS或漏极扩展（DENMOS）高功率晶体管，其中保护器件（SCR）和NMOS或DENMOS晶体管集成在一起，可以节省硅的空间。 通过向高功率NMOS（DENMOS）晶体管的n阱（漏极）添加p +扩散使得加入的p +扩散与上述n阱和硅晶片的p-衬底一起形成，可以实现积分 SCR的两个晶体管之一。 SCR的低触发电压通过使SCR的第二寄生npn晶体管与NMOS（DENMOS）晶体管并联，通过共享n阱（集电极/漏极），p-衬底（基极/沟道区）， 和p-基底中相邻的n +扩散（发射极/源极）。 通过使用DENMOS晶体管的罐式氧化法获得高HBM ESD通过电压。

公开(公告)号：US06590262B2

公开(公告)日：2003-07-08

申请号：US10082729

申请日：2002-02-26

Applicant: Jyh-Min Jiang ,  Kuo-Chio Liu ,  Jian-Hsing Lee ,  Ruey-Hsin Liu

Inventor： Jyh-Min Jiang ,  Kuo-Chio Liu ,  Jian-Hsing Lee ,  Ruey-Hsin Liu

IPC: H01L2701

CPC classification number: H01L27/0266 ,  H01L27/0288 ,  H01L29/7436 ,  H01L29/87

Abstract: A device layout is disclosed for an ESD device for protecting NMOS high voltage transistors where the SCR protection device and the two NMOS transistors are integrated. The two NMOS transistors share an n-type doped drain (ndd) area which has implanted two n+ drains, one for each of the two transistors and a p+ diffusion separates the two n+ drains. Furthermore, the ndd area has implanted an n-well which extends from halfway under the first n+ drain to halfway under the second n+ drain. In addition, the depth of the n-well exceeds the depth of the ndd area. The added p+ diffusion together with the ndd area and the p-substrate of the silicon wafer create the parasitic pnp transistors of the SCR. The shared ndd area together with the n+ sources of the NMOS transistors creates the SCR's two parasitic npn transistors. The low triggering voltage of the SCR is achieved by the combination of the n-well, the ndd area, the p+diffusion between the two drains, and by having the two parasitic npn transistors paralleled.

Abstract translation: 公开了用于保护NMOS高压晶体管的ESD器件的器件布局，其中SCR保护器件和两个NMOS晶体管被集成。 两个NMOS晶体管共享一个n型掺杂漏极（ndd）区域，其已经注入了两个n +漏极，一个用于两个晶体管中的每一个，p +扩散分离两个n +漏极。 此外，ndd区域已经注入n阱，其从第n +漏极下方的中途延伸到第二n +漏极下方的中间。 另外，n阱的深度超过ndd区域的深度。 添加的p +扩散与硅晶片的ndd区和p基底一起产生SCR的寄生pnp晶体管。 共享的ndd区域与NMOS晶体管的n +源产生SCR两个寄生npn晶体管。 SCR的低触发电压通过n阱，ndd面积，两个漏极之间的p +扩散以及两个寄生npn晶体管并联的组合来实现。

公开(公告)号：US06323074B1

公开(公告)日：2001-11-27

申请号：US09557394

申请日：2000-04-24

Applicant: Jyh-Min Jiang ,  Kuo-Chio Liu ,  Jian-Hsing Lee ,  Ruey-Hsin Liu

Inventor： Jyh-Min Jiang ,  Kuo-Chio Liu ,  Jian-Hsing Lee ,  Ruey-Hsin Liu

IPC: H01L218238

CPC classification number: H01L27/0266 ,  H01L27/0288 ,  H01L29/7436 ,  H01L29/87

Abstract: A device layout is disclosed for an ESD device for protecting NMOS high voltage transistors where the SCR protection device and the two NMOS transistors are integrated. The two NMOS transistors share an n-type doped drain (ndd) area which has implanted two n+ drains, one for each of the two transistors and a p+ diffusion separates the two n+ drains. Furthermore, the ndd area has implanted an n-well which extends from halfway under the first n+ drain to halfway under the second n+ drain. In addition, the depth of the n-well exceeds the depth of the ndd area. The added p+diffusion together with the ndd area and the p-substrate of the silicon wafer create the parasitic pnp transistors of the SCR. The shared ndd area together with the n+ sources of the NMOS transistors creates the SCR's two parasitic npn transistors. The low triggering voltage of the SCR is achieved by the combination of the n-well, the ndd area, the p+diffusion between the two drains, and by having the two parasitic npn transistors paralleled.

Abstract translation: 公开了用于保护NMOS高压晶体管的ESD器件的器件布局，其中SCR保护器件和两个NMOS晶体管被集成。 两个NMOS晶体管共享一个n型掺杂漏极（ndd）区域，其已经注入了两个n +漏极，一个用于两个晶体管中的每一个，p +扩散分离两个n +漏极。 此外，ndd区域已经注入n阱，其从第n +漏极下方的中途延伸到第二n +漏极下方的中间。 另外，n阱的深度超过ndd区域的深度。 添加的p +扩散与硅晶片的ndd区和p基底一起产生SCR的寄生pnp晶体管。 共享的ndd区域与NMOS晶体管的n +源产生SCR两个寄生npn晶体管。 SCR的低触发电压通过n阱，ndd面积，两个漏极之间的p +扩散以及两个寄生npn晶体管并联的组合来实现。

公开(公告)号：US20110084391A1

公开(公告)日：2011-04-14

申请号：US12842753

申请日：2010-07-23

Applicant: Shyh-Wei Cheng ,  Pin-Shyne Chin ,  Kuo-Chio Liu ,  Che-Jung Chu ,  Ming-Chang Hsieh ,  Hung-Lin Chen ,  Tian Sheng Lin

Inventor： Shyh-Wei Cheng ,  Pin-Shyne Chin ,  Kuo-Chio Liu ,  Che-Jung Chu ,  Ming-Chang Hsieh ,  Hung-Lin Chen ,  Tian Sheng Lin

IPC: H01L23/532

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/0233 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05022 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/13006 ,  H01L2224/13023 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2224/05552

Abstract: An integrated circuit structure includes a semiconductor substrate; a first titanium layer over the semiconductor substrate, wherein the first titanium layer has a first thickness less than 130 Å; a first titanium nitride layer over and contacting the first titanium layer; and an aluminum-containing layer over and contacting the first titanium nitride layer.

Abstract translation: 集成电路结构包括半导体衬底; 半导体衬底上的第一钛层，其中第一钛层具有小于130的第一厚度; 在第一钛层上方并与第一钛层接触的第一氮化钛层; 以及与第一氮化钛层接触的含铝层。

公开(公告)号：US06569730B2

公开(公告)日：2003-05-27

申请号：US10091990

申请日：2002-03-06

Applicant: Jun-Lin Tsai ,  Ruey-Hsin Liu ,  Jei-Feng Hwang ,  Kuo-Chio Liu

Inventor： Jun-Lin Tsai ,  Ruey-Hsin Liu ,  Jei-Feng Hwang ,  Kuo-Chio Liu

IPC: H01L218249

CPC classification number: H01L29/66272 ,  H01L29/0821 ,  H01L29/7322

Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.

公开(公告)号：US20050194647A1

公开(公告)日：2005-09-08

申请号：US10793972

申请日：2004-03-05

Applicant: Hung-Chih Tsai ,  Chien-Chih Chou ,  Ying-Ting Chang ,  Che-Jung Chu ,  Kuo-Chio Liu

Inventor： Hung-Chih Tsai ,  Chien-Chih Chou ,  Ying-Ting Chang ,  Che-Jung Chu ,  Kuo-Chio Liu

IPC: H01L31/113

CPC classification number: H01L29/7835 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/456

Abstract: A high voltage PMOS device having an improved breakdown voltage is achieved. An asymmetrical high voltage integrated circuit structure comprises a gate electrode on a substrate and source and drain regions within the substrate on either side and adjacent to the gate electrode wherein the source region is encompassed by an n-well. A symmetrical high voltage integrated circuit structure comprises a gate electrode on a substrate, source and drain regions within the substrate on either side and adjacent to the gate electrode, and an n-well in the substrate underlying the gate electrode. The n-well in both structures shifts the breakdown point from the silicon surface to the bottom of the source or drain regions.

Abstract translation: 实现了具有改善的击穿电压的高电压PMOS器件。 不对称的高压集成电路结构包括衬底上的栅极电极和位于栅极电极的任一侧和邻近的衬底内的源极和漏极区域，其中源极区域被n阱包围。 对称的高压集成电路结构包括衬底上的栅极电极，位于栅极电极的任一侧和邻近衬底内的源极和漏极区域以及位于栅极电极下方的衬底中的n-阱。 两个结构中的n阱将击穿点从硅表面移动到源极或漏极区域的底部。

公开(公告)号：US06423590B2

公开(公告)日：2002-07-23

申请号：US09846538

申请日：2001-05-02

Applicant: Jun-Lin Tsai ,  Ruey-Hsin Lin ,  Jei-Feng Hwang ,  Kuo-Chio Liu

Inventor： Jun-Lin Tsai ,  Ruey-Hsin Lin ,  Jei-Feng Hwang ,  Kuo-Chio Liu

IPC: H01L2100

CPC classification number: H01L29/66272 ,  H01L29/0821 ,  H01L29/7322

Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.

Abstract translation: 公开了一种用于高电压双极晶体管的新设计。 代替埋置的子集电极（在NPN器件中将为N +），使用掩埋的P +层。 该P +层的存在导致其本身和双极基底之间的夹断。 这样可以实现更高的击穿电压。 特别地，该装置不会在作为常规装置的弱点的基极 - 集电极结的底部分解。 对该装置的制造方法进行说明。 这个新工艺的一个特点是在P +层上生长的N型外延层只是传统器件中其对应厚度的大约一半。 该工艺与传统的BiCMOS工艺完全兼容，成本较低。

公开(公告)号：US06211028B1

公开(公告)日：2001-04-03

申请号：US09245560

申请日：1999-02-05

Applicant: Jun-Lin Tsai ,  Ruey-Hsing Liu ,  Chiou-Shian Peng ,  Kuo-Chio Liu

Inventor： Jun-Lin Tsai ,  Ruey-Hsing Liu ,  Chiou-Shian Peng ,  Kuo-Chio Liu

IPC: H01L21331

CPC classification number: H01L29/66272 ,  H01L29/1004 ,  H01L29/732

Abstract: A bipolar transistor is described whose I-V curve is such that it operates in two regions, one having low gain and low power consumption and another having higher gain and better current driving ability. Said transistor has a base region made up of two sub regions, the region closest to the emitter having a resistivity about an order a magnitude lower than the second region (which interfaces with the collector). A key feature of the invention is that the region closest to the collector is very uniformly doped, i.e. there is no gradient or built-in field present. In order to produce such a region, epitaxial growth along with boron doping is used rather than more conventional techniques such as ion implantation and/or diffusion.

Abstract translation: 描述了一种双极性晶体管，其I-V曲线使得其工作在两个区域中，一个具有低增益和低功耗，另一个具有较高的增益和更好的电流驱动能力。 所述晶体管具有由两个子区域构成的基极区域，最靠近发射极的区域的电阻率大约低于第二区域（与集电极接口）的数量级。 本发明的关键特征是最靠近集电极的区域是非常均匀的掺杂的，即没有梯度或内置的场存在。 为了制造这样的区域，使用外延生长以及硼掺杂，而不是诸如离子注入和/或扩散的更常规的技术。