公开(公告)号：US10971586B2

公开(公告)日：2021-04-06

申请号：US16204474

申请日：2018-11-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jung-Chan Yang ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Lee-Chung Lu ,  Li-Chun Tien

IPC: H01L29/06 ,  H01L27/092 ,  H01L27/02 ,  H01L21/033 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  G06F30/392

Abstract: In at least one cell region, a semiconductor device includes fins and at least one overlying gate structure. The fins (dummy and active) are substantially parallel to a first direction. Each gate structure is substantially parallel to a second direction (which is substantially perpendicular to the first direction). First and second active fins have corresponding first and second conductivity types. Each cell region, relative to the second direction, includes: a first active region which includes a sequence of three or more consecutive first active fins located in a central portion of the cell region; a second active region which includes one or more second active fins located between the first active region and a first edge of the cell region; and a third active region which includes one or more second active fins located between the first active region and a second edge of the cell region.

公开(公告)号：US10943050B2

公开(公告)日：2021-03-09

申请号：US16514210

申请日：2019-07-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Cheok-Kei Lei ,  Jerry Chang Jui Kao ,  Chi-Lin Liu ,  Hui-Zhong Zhuang ,  Zhe-Wei Jiang ,  Chien-Hsing Li

IPC: G06F30/398 ,  G06F30/392 ,  G06F30/367

Abstract: A method of making an integrated circuit includes operations to identify reverse signal nets of the circuit layout, determine when the conductive lines to the reverse signal net have parasitic capacitance, and determine how to adjust an integrated circuit layout to reduce the parasitic capacitance of the conductive lines to the reverse signal net. The method further includes an operation to determine whether to move one of the conductive lines in the integrated circuit layout, and an operation to determine whether to insert an isolation structure between the conductive lines of the reverse signal net having parasitic capacitance.

公开(公告)号：US10885254B2

公开(公告)日：2021-01-05

申请号：US16397064

申请日：2019-04-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Li-Chun Tien

IPC: G06F30/392 ,  H01L27/02 ,  H01L27/092

Abstract: A method of manufacturing an integrated circuit includes manufacturing a first set of conductive features by a first mask, positioning a set of gates in a second direction, manufacturing a second set of conductive features by a second mask, and electrically coupling a first portion of the set of gates to a second portion of the set of gates. The first and second set of conductive features is in a first direction and a first layer. The set of gates is in a second layer. The first portion of the set of gates corresponds to a gate terminal of a first n-type transistor, the second portion of the set of gates corresponds to a gate terminal of a first p-type transistor, the first n-type transistor being part of a first transmission gate, and the first p-type transistor being part of a second transmission gate.

公开(公告)号：US10783313B2

公开(公告)日：2020-09-22

申请号：US16549943

申请日：2019-08-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Kuang-Ching Chang ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Jung-Chan Yang

IPC: G06F17/50 ,  H01L25/00 ,  H03K19/00 ,  H03K17/00 ,  G06F30/398 ,  G06F111/04 ,  G06F30/347 ,  H03K19/018 ,  G06F30/3947 ,  H03K19/0175 ,  H03K19/0185 ,  H03K17/687 ,  G06F30/3953 ,  H03K19/17736 ,  G06F30/392

Abstract: A method of preparing an integrated circuit device design including analyzing a preliminary device layout to identify a vertical abutment between a first cell and a second cell, the locations of, and spacing between, internal metal cuts within the first and second cells, indexing the second cell relative to the first cell by N CPP to define one or more intermediate device layouts to define a modified device layout with improved internal metal cut spacing in order to suppress BGE and LE.

公开(公告)号：US20200257842A1

公开(公告)日：2020-08-13

申请号：US16860714

申请日：2020-04-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tung-Heng Hsieh ,  Sheng-Hsiung Wang ,  Hui-Zhong Zhuang ,  Yu-Cheng Yeh ,  Tsung-Chieh Tsai ,  Juing-Yi Wu ,  Liang-Yao Lee ,  Jyh-Kang Ting

IPC: G06F30/392 ,  G06F30/398 ,  G06F30/394 ,  H01L27/118 ,  H01L27/02

Abstract: A post placement abutment treatment for cell row design is provided. In an embodiment a first cell and a second cell are placed in a first cell row and a third cell and a fourth cell are placed into a second cell row. After placement vias connecting power and ground rails to the underlying structures are analyzed to determine if any can be merged or else removed completely. By merging and removing the closely placed vias, the physical limitations of photolithography may be by-passed, allowing for smaller structures to be formed.

公开(公告)号：US10734377B2

公开(公告)日：2020-08-04

申请号：US15782183

申请日：2017-10-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kam-Tou Sio ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Hui-Zhong Zhuang ,  Jiann-Tyng Tzeng ,  Yi-Hsun Chiu

IPC: H01L27/02 ,  H01L27/085 ,  H01L27/118 ,  H01L27/092 ,  H01L21/8238

Abstract: An integrated circuit structure includes a first well, and a first and a second set of implants. The first well includes a first dopant type, a first portion extending in a first direction and having a first width, and a second portion adjacent to the first portion. The second portion extends in the first direction and has a second width greater than the first width. The first set of implants are in the first portion of the first well, and the second set of implants are in the second portion of the first well. At least one implant of the first set of implants being configured to be coupled to a first supply voltage. Each implant of the second set of implants having a second dopant type different from a first dopant type of the first set of implants.

公开(公告)号：US10664639B2

公开(公告)日：2020-05-26

申请号：US15971646

申请日：2018-05-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tung-Heng Hsieh ,  Sheng-Hsiung Wang ,  Hui-Zhong Zhuang ,  Yu-Cheng Yeh ,  Tsung-Chieh Tsai ,  Juing-Yi Wu ,  Liang-Yao Lee ,  Jyh-Kang Ting

IPC: G06F17/50 ,  G06F30/392 ,  G06F30/394 ,  H01L27/118 ,  H01L27/02 ,  G06F30/398

Abstract: A post placement abutment treatment for cell row design is provided. In an embodiment a first cell and a second cell are placed in a first cell row and a third cell and a fourth cell are placed into a second cell row. After placement vias connecting power and ground rails to the underlying structures are analyzed to determine if any can be merged or else removed completely. By merging and removing the closely placed vias, the physical limitations of photolithography may be by-passed, allowing for smaller structures to be formed.

公开(公告)号：US20200074044A1

公开(公告)日：2020-03-05

申请号：US16674869

申请日：2019-11-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shih-Wei Peng ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Hui-Zhong Zhuang ,  Jiann-Tyng Tzeng ,  Shun Li Chen ,  Wei-Cheng Lin

IPC: G06F17/50 ,  H01L27/02 ,  H01L27/118

Abstract: A method of forming an integrated circuit includes generating, by a processor, a layout design of the integrated circuit based on a set of design rules and manufacturing the integrated circuit based on the layout design. The generating of the layout design includes generating a set of active region layout patterns extending in a first direction, generating a set of gate layout patterns extending in a second direction, and generating a cut feature layout pattern extending in the first direction, overlapping at least a first gate layout pattern of the set of gate layout patterns, being separated from the set of active region layout patterns in the second direction by at least a first distance. The first distance satisfying a first design rule of the set of design rules.

公开(公告)号：US20190279975A1

公开(公告)日：2019-09-12

申请号：US16420919

申请日：2019-05-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Te Lin ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Pin-Dai Sue ,  Li-Chun Tien

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/423 ,  G06F17/50

Abstract: A layout includes a plurality of cells and at least one dummy gate electrode continuously extends across the cells. Since the dummy gate electrode is electrically conductive, the dummy gate electrode can be utilized for interconnecting the cells. That is, some signals may travel through the dummy gate electrode rather than through a metal one line or a metal two line. Therefore, an amount of metal one lines and/or metal two lines for interconnecting the cells can be reduced

公开(公告)号：US10380315B2

公开(公告)日：2019-08-13

申请号：US15682885

申请日：2017-08-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hui-Zhong Zhuang ,  Ting-Wei Chiang ,  Lee-Chung Lu ,  Li-Chun Tien ,  Shun Li Chen

IPC: G06F17/50 ,  H01L27/02 ,  H01L27/118

Abstract: An IC structure includes a cell, a first rail and a second rail. The cell includes a first and a second active region and a first gate structure. The first and second active region extend in a first direction and is located at a first level. The second active region is separated from the first active region in a second direction. The first gate structure extends in the second direction, overlaps the first and second active region, and is located at a second level. The first rail extends in the first direction, overlaps the first active region, is configured to supply a first supply voltage, and is located at a third level. The second rail extends in the first direction, overlaps the second active region, is located at the third level, separated from the first rail in the second direction, and is configured to supply a second supply voltage.