公开(公告)号：US20150115990A1

公开(公告)日：2015-04-30

申请号：US14590502

申请日：2015-01-06

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/26

CPC classification number: G01R31/318572 ,  G01R31/2607 ,  G01R31/3177 ,  G01R31/318513 ,  G01R31/318552 ,  G01R31/318558 ,  G01R31/318594 ,  H01J37/3007 ,  H01J37/3171 ,  H01J2237/15 ,  H01J2237/30472

Abstract: A test control port (TCP) includes a state machine SM, an instruction register IR, data registers DRs, a gating circuit and a TDO MX. The SM inputs TCI signals and outputs control signals to the IR and to the DR. During instruction or data scans, the IR or DRs are enabled to input data from TDI and output data to the TDO MX and the top surface TDO signal. The bottom surface TCI inputs may be coupled to the top surface TCO signals via the gating circuit. The top surface TDI signal may be coupled to the bottom surface TDO signal via TDO MX. This allows concatenating or daisy-chaining the IR and DR of a TCP of a lower die with an IR and DR of a TCP of a die stacked on top of the lower die.

Abstract translation: 测试控制端口（TCP）包括状态机SM，指令寄存器IR，数据寄存器DR，门控电路和TDO MX。 SM输入TCI信号并向IR和DR输出控制信号。 在指令或数据扫描期间，IR或DR可用于从TDI输入数据，并将数据输出到TDO MX和顶表面TDO信号。 底表面TCI输入可以经由选通电路耦合到顶表面TCO信号。 顶表面TDI信号可以经由TDO MX耦合到底表面TDO信号。 这允许将下模的TCP的IR和DR串联或菊花链链接到下模的顶部上的管芯的IR的IR和DR。

公开(公告)号：US09021322B2

公开(公告)日：2015-04-28

申请号：US14089069

申请日：2013-11-25

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/317 ,  G01R31/3185 ,  G11C29/00 ,  G11C29/02 ,  G11C29/48 ,  G11C29/32

CPC classification number: G01R31/3177 ,  G01R31/31715 ,  G01R31/318505 ,  G01R31/318511 ,  G01R31/318533 ,  G01R31/318558 ,  G01R31/318572 ,  G01R31/318594 ,  G11C29/006 ,  G11C29/022 ,  G11C29/48 ,  G11C2029/3202

Abstract: The peripheral circuitry (350, 360, ESD, BH) of an integrated circuit die on a wafer is tested without physically contacting the bond pads of the die.

公开(公告)号：US08977920B2

公开(公告)日：2015-03-10

申请号：US13889004

申请日：2013-05-07

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/3185

CPC classification number: G01R31/3172 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318555

Abstract: A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The reduced device test interface is achieved using a double data rate (DDR) signaling technique between the tester and the device. The DDR test interface allows the tester to interface to test circuits within the device, such as IEEE 1500 and/or IEEE 1149.1 test circuits, to provide high test data bandwidth to the test circuits using a minimum of test interface signals. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. Additional features and embodiments of the device test architecture and reduced test interface are also disclosed.

Abstract translation: 提供了一种器件测试架构和一个简化的器件测试接口，以便能够高效地测试器件内嵌入的内核和其他电路。 使用测试仪和设备之间的双重数据速率（DDR）信令技术实现了减少的设备测试接口。 DDR测试接口允许测试仪与设备内的测试电路（如IEEE 1500和/或IEEE 1149.1测试电路）进行接口，使用最少的测试接口信号为测试电路提供高测试数据带宽。 测试架构包括比较电路，允许比较要在设备内执行的测试响应数据。 测试架构还包括用于存储测试响应比较结果的存储器。 测试架构包括一个可编程测试控制器，通过简单地从外部测试仪向可编程测试控制器输入指令，允许各种测试控制操作。 还公开了设备测试架构和降低的测试接口的附加特征和实施例。

公开(公告)号：US08972810B2

公开(公告)日：2015-03-03

申请号：US14444236

申请日：2014-07-28

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/317 ,  G06F11/267 ,  G01R31/3185

CPC classification number: G01R31/31723 ,  G01R31/317 ,  G01R31/31705 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318533 ,  G01R31/318536 ,  G01R31/318591 ,  G01R31/318597 ,  G06F11/267

Abstract: The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.

Abstract translation: 本公开描述了使用JTAG Tap的TMS和/或TCK终端作为通用串行输入/输出（I / O）曼彻斯特编码通信终端。 Tap的TMS和/或TCK终端可以用作串行I / O通信通道; （1）IC和外部控制器，（2）在第一和第二IC之间，或（3）IC内的第一和第二核心电路之间。 如上所述，使用TMS和/或TCK端子作为串行I / O通道不会影响JTAG Tap的标准化操作，因为TMS和/或TCK I / O操作发生在Tap被放置在 非活跃稳态。

公开(公告)号：US20150058689A1

公开(公告)日：2015-02-26

申请号：US14508526

申请日：2014-10-07

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/2851 ,  G01R31/318544 ,  G01R31/318547 ,  G11C29/48

Abstract: A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface (202). The access is accomplished by combining the separate TDI and TMS signals from the TAP controller into a single signal and communicating the TDI and TMS signals of the single signal on the rising and falling edges of the TCK driving the DDR interface. The TAP domain may be coupled to the TAP controller in a point to point fashion or in an addressable bus fashion. The access to the TAP domain may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

Abstract translation: 一种过程和装置提供一种JTAG TAP控制器（302），以使用减少的引脚数，高速DDR接口（202）来访问设备的JTAG TAP域（106）。 通过将来自TAP控制器的单独TDI和TMS信号组合成单个信号并在驱动DDR接口的TCK的上升沿和下降沿传送单个信号的TDI和TMS信号来实现接入。 TAP域可以以点对点方式或以可寻址总线方式耦合到TAP控制器。 对TAP域的访问可用于基于JTAG的设备测试，调试，编程或其他类型的基于JTAG的操作。

公开(公告)号：US08964918B2

公开(公告)日：2015-02-24

申请号：US14337413

申请日：2014-07-22

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: H04L7/00

CPC classification number: G06F13/4291 ,  G01R31/31725 ,  G01R31/31726 ,  G01R31/318536 ,  G01R31/318594 ,  G06F1/04 ,  G06F1/06 ,  H04B1/18 ,  H04J3/0644 ,  H04L7/0008

Abstract: Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.

Abstract translation: 数据通过两个单独的电路或电路组进行通信，每个电路或电路组通过顺序地反转时钟和模式输入的作用而具有时钟和模式输入。 数据通信电路具有数据输入，数据输出，用于定时或同步数据输入和/或输出通信的时钟输入，以及用于控制数据输入和/或输出通信的模式输入。 时钟/模式信号连接到一个电路的时钟输入和另一个电路的模式输入。 模式/时钟信号连接到一个电路的模式输入和另一个电路的时钟输入。 模式和时钟信号对模式/时钟和时钟/模式信号或其反相的作用选择数据通信电路中的一个或另一个。

公开(公告)号：US08943376B2

公开(公告)日：2015-01-27

申请号：US14314430

申请日：2014-06-25

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/28 ,  G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/318536 ,  G01R31/318558 ,  G01R31/318572

Abstract: Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan circuitry and the functional inputs and outputs. The core circuitry can also be provided with built-in scan distributor, collector, and controller circuitry to avoid having to add it external of the core circuitry. With appropriately placed built-in scan distributor and collector circuits, connecting together the functional inputs and outputs of the core circuitry also connects together the scan distributor and collector circuitry in each core. This can provide a hierarchy of scan circuitry and reduce the need for separate test interconnects and multiplexers.

公开(公告)号：US08938652B2

公开(公告)日：2015-01-20

申请号：US13941732

申请日：2013-07-15

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/31722 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318541 ,  G01R31/318558

Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. 41-49, provides for selectively using either the 5 signal interface of FIG. 41 or the 3 signal interface of FIG. 8.

Abstract translation: 本公开描述了可以在集成电路中的集成电路或嵌入式核心上使用的减少的引脚总线。 总线可用于串行访问电路，其中IC或引脚上的引脚的可用性受限制。 总线可用于各种串行通信操作，例如但不限于IC或核心设计的串行通信相关测试，仿真，调试和/或跟踪操作。 本公开的其他方面包括使用减少的针脚总线用于仿真，调试和跟踪操作以及功能操作。 在本公开的第五方面中，一种接口选择电路， 图41-49提供了选择性地使用图5的5信号接口。 41或图3的3信号接口。 8。

公开(公告)号：US20150012789A1

公开(公告)日：2015-01-08

申请号：US14494787

申请日：2014-09-24

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/317 ,  G01R31/3177 ,  G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/2815 ,  G01R31/3172 ,  G01R31/31723 ,  G01R31/31724 ,  G01R31/31727 ,  G01R31/318541 ,  G01R31/318555 ,  G01R31/318558 ,  G01R31/318572 ,  G06F11/3656

Abstract: An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations.

Abstract translation: 优化的JTAG接口用于访问集成电路中的JTAG Tap Domains。 该接口需要比传统JTAG接口更少的引脚，因此比在引脚可用性有限的集成电路上的传统JTAG接口更为适用。 该接口可以用于各种串行通信操作，例如但不限于与串行通信相关的集成电路测试，仿真，调试和/或跟踪操作。

公开(公告)号：US20140359388A1

公开(公告)日：2014-12-04

申请号：US14460855

申请日：2014-08-15

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/3173

CPC classification number: G01R31/31723 ,  G01R31/2851 ,  G01R31/3172 ,  G01R31/31724 ,  G01R31/3173 ,  G01R31/3177 ,  G01R31/318563 ,  G01R31/318575

Abstract: A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths. Select and enable signals control the operation of the scan path sections. The output of each scan path passes through a multiplexer to compare circuits on the semiconductor substrate. The compare circuits also receive expected data and mask data. The compare circuits provide a fail flag output from the semiconductor substrate.

Abstract translation: 扫描测试架构通过将串行扫描路径选择性地分成较短的部分来促进半导体电路的低功率测试。 部分之间的多路复用器控制将部分连接到更长或短路的路径。 选择并启用信号控制扫描路径部分的操作。 每个扫描路径的输出通过多路复用器来比较半导体衬底上的电路。 比较电路还接收预期数据和掩模数据。 比较电路提供从半导体衬底输出的故障标志。