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121.发明授权公开(公告)号：US07753296B2
公开(公告)日：2010-07-13
申请号：US12372542
申请日：2009-02-17
CPC分类号： B08B17/06 , B01J2/16 , B02C19/065 , B02C23/10 , B07B7/083 , G03G9/0817
摘要： A pulverization/classification apparatus including a cylindrical vessel having an inner wall, on a surface of which a layer including a release agent is located; a pulverizer configured to pulverize a material such as toner raw materials in the cylindrical vessel using a compressed air to prepare a particulate material; and a classifier configured to classify the particulate toner material to prepare a powder of the material. Alternatively, the inner wall of the cylindrical vessel has a circumferentially projected portion. A method for manufacturing a powder such as toners using the pulverization/classification apparatus is also provided.
摘要翻译： 一种粉碎/分级装置，包括具有内壁的圆柱形容器，其表面上设置有包含脱模剂的层; 粉碎机，其构造成使用压缩空气粉碎所述圆筒形容器中的调色剂原料的材料，以制备颗粒材料; 以及分级器，其被配置为对所述颗粒调色剂材料进行分类以制备所述材料的粉末。 或者，圆柱形容器的内壁具有周向突出部分。 还提供了使用粉碎/分级装置制造诸如调色剂的粉末的方法。
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公开(公告)号：US07722584B2
公开(公告)日：2010-05-25
申请号：US11768384
申请日：2007-06-26
IPC分类号： A61M1/00
CPC分类号： A61F5/451 , A61B5/208 , A61M1/0001 , A61M1/0025 , A61M1/005 , A61M2202/0496 , A61M2205/3393
摘要： An automatic urine collection apparatus includes a collection container for accumulating urine transferred from a urine receiver through a tube and a main body for supporting the collection container, wherein the main body includes a suction pump for sucking the urine received by the urine receiver and carrying the urine to the collection container, a mass sensor for measuring the urine accumulated in the collection container, a control board for calculating a volume of the urine based on the measured mass of the urine, and an indicator for indicating the calculated volume of the urine.
摘要翻译： 一种自动尿液收集装置，包括：收集容器，用于积聚从尿液接收器经由管传送的尿液和用于支撑收集容器的主体，其中，所述主体包括抽吸泵，所述抽吸泵吸收由所述尿液接收器接收的尿液， 尿液到收集容器，用于测量收集容器中积聚的尿液的质量传感器，用于根据测量的尿液量计算尿液体积的控制板和用于指示计算出的尿量的指示器。
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公开(公告)号：US20090211992A1
公开(公告)日：2009-08-27
申请号：US11911207
申请日：2005-04-13
CPC分类号： C02F1/488 , B01D33/073 , B01D33/37 , B01D35/06 , C02F1/5236 , C02F1/56
摘要： For providing a water filtration purifying apparatus and a method thereof, enabling to reduce the manufacturing costs of the apparatus as a whole, by combining a function of filtration and a function of separation/concentration, the filtration function and the separation/concentration are separated, in the structure thereof. Thus, since all sewage waters generated in respective filtration separators can be collected by only one (1) set of a magnetic separator, even if there are plural number of the filtration separators, it is possible to dissolve a problem of rising up the costs of the apparatus, as a whole. With this, it is possible to provide a water filtration purifying apparatus, for enabling high water-quality purification and also reducing low manufacturing costs thereof, by further small-sizing the magnetic separating portion.
摘要翻译： 为了提供一种水过滤净化装置及其方法，通过结合过滤功能和分离/浓缩功能，可以将整个装置的制造成本降低，将过滤功能和分离/浓缩分离， 在其结构中。 因此，由于在各个过滤分离器中产生的所有污水只能由一个（1）个磁选机收集，所以即使有多个过滤分离器也可以解决上述问题， 该装置作为一个整体。 由此，通过进一步小型化磁分离部，可以提供一种能够实现高水质净化的水过滤净化装置，并且还能降低制造成本。
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124.发明申请公开(公告)号：US20090159730A1
公开(公告)日：2009-06-25
申请号：US12372542
申请日：2009-02-17
IPC分类号： B02C19/06
CPC分类号： B08B17/06 , B01J2/16 , B02C19/065 , B02C23/10 , B07B7/083 , G03G9/0817
摘要： A pulverization/classification apparatus including a cylindrical vessel having an inner wall, on a surface of which a layer including a release agent is located; a pulverizer configured to pulverize a material such as toner raw materials in the cylindrical vessel using a compressed air to prepare a particulate material; and a classifier configured to classify the particulate toner material to prepare a powder of the material. Alternatively, the inner wall of the cylindrical vessel has a circumferentially projected portion. A method for manufacturing a powder such as toners using the pulverization/classification apparatus is also provided.
摘要翻译： 一种粉碎/分级装置，包括具有内壁的圆柱形容器，其表面上设置有包含脱模剂的层; 粉碎机，其构造成使用压缩空气粉碎所述圆筒形容器中的调色剂原料的材料，以制备颗粒材料; 以及分级器，其被配置为对所述颗粒调色剂材料进行分类以制备所述材料的粉末。 或者，圆柱形容器的内壁具有周向突出部分。 还提供了使用粉碎/分级装置制造诸如调色剂的粉末的方法。
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公开(公告)号：US20090100231A1
公开(公告)日：2009-04-16
申请号：US11816858
申请日：2006-02-08
IPC分类号： G06F12/08
CPC分类号： G06F12/12 , G06F12/0802 , G06F12/0893
摘要： A cache memory system which readily accepts software control for processing includes: a cache memory provided between a processor and memory; and a TAC (Transfer and Attribute Controller) for controlling the cache memory. The TAC receives a command which indicates a transfer and an attribute operation of cache data and a target for the operation, resulting from the execution of a predetermined instruction by the processor, so as to request the operation indicated by the command against the address to the cache memory.
摘要翻译： 容易接受用于处理的软件控制的高速缓冲存储器系统包括：设置在处理器和存储器之间的高速缓存存储器; 以及用于控制高速缓冲存储器的TAC（传送和属性控制器）。 TAC接收指示由处理器执行预定指令而产生的高速缓存数据的传送和属性操作以及用于操作的目标，以便请求针对该地址的命令所指示的操作 高速缓存存储器。
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公开(公告)号：US20090077318A1
公开(公告)日：2009-03-19
申请号：US11910831
申请日：2006-03-17
申请人： Takao Yamamoto , Tetsuya Tanaka , Ryuta Nakanishi , Masaitsu Nakajima , Keisuke Kaneko , Hazuki Okabayashi
发明人： Takao Yamamoto , Tetsuya Tanaka , Ryuta Nakanishi , Masaitsu Nakajima , Keisuke Kaneko , Hazuki Okabayashi
CPC分类号： G06F12/0875 , G06F12/0848 , G06F12/0888
摘要： A cache memory of the present invention includes a second cache memory that is operated in parallel with a first cache memory, a judgment unit which, when a cache miss occurs in both of the first cache memory and the second cache memory, makes a true or false judgment relating to an attribute of data for which memory access resulted in the cache miss, and a controlling unit which stores memory data in the second cache memory when a judgment of true is made, and stores the memory data in the first cache memory when a judgment of false is made.
摘要翻译： 本发明的高速缓存存储器包括与第一高速缓存存储器并行操作的第二高速缓冲存储器，当在第一高速缓冲存储器和第二高速缓冲存储器两者中发生高速缓存未命中时，判断单元都是真的或 关于存储器访问导致高速缓存未命中的数据的属性的错误判断，以及当进行判断时将存储器数据存储在第二高速缓冲存储器中的控制单元，并且将存储器数据存储在第一高速缓冲存储器中 做出了错误的判断。
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公开(公告)号：US07454575B2
公开(公告)日：2008-11-18
申请号：US10583773
申请日：2004-12-21
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F12/0886 , G06F12/127
摘要： The cache memory in the present invention is a cache entry having, in a correspondence with a cache entry which holds a data unit of caching, a valid flag indicating whether or not the cache entry is valid, and a dirty flag indicating whether or not the cache entry has been written into. The cache memory in the present invention includes an altering unit which, based on an instruction from a processor, sets, in the cache entry, an address serving as a tag and sets the valid flag, without loading data from a memory, or resets the dirty flag in a state in which the cache entry holds rewritten data that has not been written back.
摘要翻译： 本发明的高速缓冲存储器是具有与保存缓存的数据单位的高速缓存条目相对应的高速缓存条目，表示高速缓存条目是否有效的有效标志，以及指示是否 缓存条目已经写入。 本发明的高速缓冲存储器包括：改变单元，其基于来自处理器的指令，在高速缓存条目中设置用作标签的地址，并且设置有效标志，而不从存储器加载数据，或者重置 在高速缓存条目保存未被写回的重写数据的状态下的脏标志。
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公开(公告)号：US20080209162A1
公开(公告)日：2008-08-28
申请号：US12110491
申请日：2008-04-28
申请人： Kazuya Furukawa , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazushi Kurata , Shigeki Fujii , Toshio Sugimura
发明人： Kazuya Furukawa , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazushi Kurata , Shigeki Fujii , Toshio Sugimura
IPC分类号： G06F9/30
CPC分类号： G06F9/4881 , G06F9/3851 , G06F9/3867 , G06F9/462
摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.
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129.发明授权Processor and compiler for decoding an instruction and executing the decoded instruction with conditional execution flags 失效处理器和编译器，用于解码指令并用条件执行标志执行解码指令公开(公告)号：US07380112B2
公开(公告)日：2008-05-27
申请号：US10805381
申请日：2004-03-22
申请人： Hazuki Okabayashi , Tetsuya Tanaka , Taketo Heishi , Hajime Ogawa
发明人： Hazuki Okabayashi , Tetsuya Tanaka , Taketo Heishi , Hajime Ogawa
CPC分类号： G06F9/30072 , G06F8/447 , G06F9/325
摘要： The present invention provides a processor which has a small-scale circuit and is capable of executing loop processing at a high speed while consuming a small amount of power. When the processor decodes an instruction “jloop C6,C1:C4,TAR,Ra”, the processor (i) sets a conditional flag C4 to 0 when the value of a register Ra is smaller than 0, (ii) moves the value of a conditional flag C2 to a conditional flag C1, moves the value of a conditional flag C3 to the conditional flag C2, and moves the value of the conditional flag C4 to the conditional flags C3 and C6, (iii) adds −1 to the register Ra and stores the result into the register Ra, and (iv) branches to an address specified by a branch register (TAR). When not filled with a branch target instruction, the jump buffer will be filled with a branch target instruction.
摘要翻译： 本发明提供了一种具有小规模电路并且能够在消耗少量功率的同时高速执行循环处理的处理器。 当处理器解码指令“jloop C 6，C 1：C 4，TAR，Ra”时，当寄存器Ra的值小于0时，处理器（i）将条件标志C 4设置为0，（ii） 将条件标志C 2的值移动到条件标志C1，将条件标志C 3的值移动到条件标志C 2，并将条件标志C 4的值移动到条件标志C 3和C 6，（iii）向寄存器Ra添加-1，并将结果存储到寄存器Ra中，（iv）分支到由分支寄存器（TAR）指定的地址。 当没有填充分支目标指令时，跳转缓冲区将用分支目标指令填充。
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公开(公告)号：US20080046688A1
公开(公告)日：2008-02-21
申请号：US11896369
申请日：2007-08-31
申请人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
发明人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
CPC分类号： G06F9/30025 , G06F9/30014 , G06F9/30021 , G06F9/30036 , G06F9/30094 , G06F9/30145 , G06F9/3016 , G06F9/30167
摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.
摘要翻译： 根据本发明的处理器包括解码单元20，操作单元40等。 当解码单元20解码指令vcchk时，操作单元40等判断条件标志寄存器（CFR）32的矢量条件标志VC 0〜VC 3（110）是否全部为零，以及（i）设置条件 当所有向量条件标志VC 0〜VC 3都为零时，分别为条件标志寄存器（CFR）32〜1和0的标志C 4和C 5，（ii）设定条件标志C 4和C 5 分别为0和1，当不是全部矢量条件标志为零时。 然后，矢量条件标志VC 0〜VC 3被存储在条件标志C 0〜C 3中。
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