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180 条记录 (耗时 0.032 秒)

    Organic light emitting diode display and method of manufacturing the same
    122.
    发明申请
    Organic light emitting diode display and method of manufacturing the same 有权
    有机发光二极管显示器及其制造方法

    公开(公告)号：US20110049523A1

    公开(公告)日：2011-03-03

    申请号：US12805702

    申请日：2010-08-16

    申请人： Jong-Hyun Choi ,  June-Woo Lee ,  Kwang-Hae Kim ,  Kyoung-Bo Kim

    发明人： Jong-Hyun Choi ,  June-Woo Lee ,  Kwang-Hae Kim ,  Kyoung-Bo Kim

    IPC分类号： H01L33/00 ,  H01L21/02 ,  H01L51/50

    CPC分类号： H01L27/1251 ,  H01L27/1225 ,  H01L27/3262

    摘要： An OLED display including a substrate main body; a first gate electrode and a second semiconductor layer; a gate insulating layer on the first gate electrode and the second semiconductor layer; a first semiconductor layer and a second gate electrode overlying the first gate electrode and the second semiconductor layer, respectively; etching stopper layers contacting portions of the first semiconductor layer; an interlayer insulating layer on the first semiconductor layer and the second gate electrode and including contact holes exposing the plurality of etching stopper layers, respectively; a first source electrode and a first drain electrode on the interlayer insulating layer and the contact holes being indirectly connected to the first semiconductor layer via the etching stopper layers or directly connected to the first semiconductor layer; and a second source electrode and a second drain electrode on the interlayer insulating layer being connected to the second semiconductor layer.

    摘要翻译： 一种OLED显示器，包括：基板主体; 第一栅电极和第二半导体层; 在第一栅电极和第二半导体层上的栅极绝缘层; 分别覆盖所述第一栅电极和所述第二半导体层的第一半导体层和第二栅电极; 蚀刻阻挡层接触第一半导体层的部分; 在所述第一半导体层和所述第二栅电极上的层间绝缘层，并且包括分别暴露所述多个蚀刻停止层的接触孔; 层间绝缘层上的第一源电极和第一漏电极，并且所述接触孔经由所述蚀刻停止层间接地连接到所述第一半导体层，或者直接连接到所述第一半导体层; 并且所述层间绝缘层上的第二源极和第二漏极连接到所述第二半导体层。

    Semiconductor integrated circuit device with dual insulation system
    125.
    发明授权
    Semiconductor integrated circuit device with dual insulation system 失效
    具有双重绝缘系统的半导体集成电路器件

    公开(公告)号：US07548108B2

    公开(公告)日：2009-06-16

    申请号：US10761239

    申请日：2004-01-22

    申请人： Jong-Hyun Choi

    发明人： Jong-Hyun Choi

    IPC分类号： H03K19/0175 ,  H03K5/02

    CPC分类号： G11C16/30 ,  G11C5/14

    摘要： A semiconductor integrated circuit device may include a first internal circuit operating at a first voltage higher than a power supply voltage of the device, and a second internal circuit operating at a second voltage lower than the first voltage. An interface circuit may be provided to restrict a voltage transferred from the first internal circuit to the second internal circuit. The first internal circuit may include a metal oxide semiconductor (MOS) transistor having a relatively thick gate insulation layer, and the second internal circuit may have a MOS transistor having a relatively thin gate insulation layer. The interface circuit, by restricting voltage, may reduce an electric field applied to the gate insulation layer of the second MOS transistor in an effort to prevent a reduction in turn-on speed of the second MOS transistor.

    摘要翻译： 半导体集成电路器件可以包括以比器件的电源电压高的第一电压工作的第一内部电路和在比第一电压低的第二电压工作的第二内部电路。 可以提供接口电路以将从第一内部电路传送的电压限制到第二内部电路。 第一内部电路可以包括具有相对较厚栅极绝缘层的金属氧化物半导体（MOS）晶体管，并且第二内部电路可以具有具有相对薄的栅极绝缘层的MOS晶体管。 接口电路通过限制电压可以减小施加到第二MOS晶体管的栅极绝缘层的电场，以便防止第二MOS晶体管的导通速度降低。

    Temperature sensor instruction signal generator and semiconductor memory device having the same
    126.
    发明授权
    Temperature sensor instruction signal generator and semiconductor memory device having the same 失效
    温度传感器指令信号发生器和具有相同功能的半导体存储器件

    公开(公告)号：US07499359B2

    公开(公告)日：2009-03-03

    申请号：US11354125

    申请日：2006-02-15

    申请人： Jong-Hyun Choi ,  Dong-Il Seo ,  Yong-Gu Kang ,  Jung-Yong Choi ,  Young-Hun Seo

    发明人： Jong-Hyun Choi ,  Dong-Il Seo ,  Yong-Gu Kang ,  Jung-Yong Choi ,  Young-Hun Seo

    IPC分类号： G11C7/00

    CPC分类号： G01K7/01

    摘要： A temperature sensor instruction signal generator, which may drive a temperature sensor, and a semiconductor memory device including the same. The temperature sensor instruction signal generator may generate an instruction signal that instruct the operation of the temperature sensor using at least one of a master clock (CLK) signal, a clock enable (CKE) signal, a row address selection (RAS) signal, a column address selection (CAS) signal, a write enable (WE) signal, and a chip selection (CS) signal, wherein the instruction signal may be enabled corresponding to at least one of a self refresh mode, an auto refresh mode, and a long tRAS mode. The semiconductor memory device may include a temperature sensor and the temperature sensor instruction signal generator.

    摘要翻译： 可以驱动温度传感器的温度传感器指令信号发生器和包括该温度传感器的半导体存储器件。 温度传感器指令信号发生器可以使用主时钟（CLK）信号，时钟使能（CKE）信号，行地址选择（RAS）信号， 列地址选择（CAS）信号，写使能（WE）信号和芯片选择（CS）信号，其中所述指令信号可以对应于自刷新模式，自动刷新模式和 长tRAS模式。 半导体存储器件可以包括温度传感器和温度传感器指令信号发生器。

    FLAT PANEL DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME
    127.
    发明申请
    FLAT PANEL DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    平板显示装置及其制造方法

    公开(公告)号：US20080224129A1

    公开(公告)日：2008-09-18

    申请号：US12047619

    申请日：2008-03-13

    申请人： Jong-Hyun Choi ,  Woo-Sik Jun

    发明人： Jong-Hyun Choi ,  Woo-Sik Jun

    IPC分类号： H01L51/56 ,  H01L21/77

    CPC分类号： H01L27/1277 ,  H01L21/02532 ,  H01L21/02672 ,  H01L27/1255 ,  H01L27/3244

    摘要： A flat panel display device, more particularly, an Organic Light Emitting Diode (OLED) display device having uniform electrical characteristics and a method of fabricating the same include: a thin film transistor of which a semiconductor layer including a source, a drain, and a channel region formed in a super grain silicon (SGS) crystallization growth region; a capacitor formed in an SGS crystallization seed region; and an OLED electrically connected to the thin film transistor. Further, a length of the channel region of the silicon layer is parallel with the growth direction in the SGS growth region to improve the electrical properties thereof.

    摘要翻译： 平板显示装置，特别是具有均匀电特性的有机发光二极管（OLED）显示装置及其制造方法包括：薄膜晶体管，其包括源极，漏极和漏极的半导体层 形成在超晶硅（SGS）结晶生长区中的沟道区; 在SGS结晶种子区域形成的电容器; 以及电连接到薄膜晶体管的OLED。 此外，硅层的沟道区域的长度与SGS生长区域中的生长方向平行，以改善其电性能。

    Input/output circuit of semiconductor memory device and input/output method thereof
    128.
    发明授权
    Input/output circuit of semiconductor memory device and input/output method thereof 有权
    半导体存储器件的输入/输出电路及其输入/输出方法

    公开(公告)号：US07397281B2

    公开(公告)日：2008-07-08

    申请号：US11348582

    申请日：2006-02-06

    申请人： Jong-Hyun Choi ,  Young-Hun Seo

    发明人： Jong-Hyun Choi ,  Young-Hun Seo

    IPC分类号： H03K19/0175

    CPC分类号： G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  H03K19/0005

    摘要： An input/output circuit for a semiconductor memory device, including a data output circuit configured to buffer output data in the semiconductor memory device in response to an input/output enable signal to output the buffered output data to an input/output signal line, a data input circuit configured to receive input data from the input/output signal line and buffer the input data to transfer the buffered input data to the semiconductor memory device, and a load controller configured to control a load on the input/output signal line in response to the input/output enable signal.

    摘要翻译： 一种用于半导体存储器件的输入/输出电路，包括数据输出电路，配置为响应于输入/输出使能信号缓冲半导体存储器件中的输出数据，以将缓冲的输出数据输出到输入/输出信号线， 数据输入电路，被配置为从输入/输出信号线接收输入数据并缓冲输入数据以将缓冲的输入数据传送到半导体存储器件;以及负载控制器，被配置为响应于控制输入/输出信号线上的负载 到输入/输出使能信号。

    Needle alignment verification circuit and method for semiconductor device
    129.
    发明授权
    Needle alignment verification circuit and method for semiconductor device 有权
    针对对准验证电路及半导体器件的方法

    公开(公告)号：US07323894B2

    公开(公告)日：2008-01-29

    申请号：US11360827

    申请日：2006-02-23

    申请人： Jong-Hyun Choi ,  Young-Hun Seo

    发明人： Jong-Hyun Choi ,  Young-Hun Seo

    IPC分类号： G01R31/02

    CPC分类号： G01R1/06794

    摘要： A needle alignment verification circuit includes a sensor pad, a first transmission line, a control element, a data pad, a second transmission line, and a response element. The sensor pad includes an insulation part and a conduction part. The first transmission line is electrically connected to the conduction part and to the interior of the semiconductor device. The control element asserts the first transmission line at a first logic state, and upon receiving the probe signal at the conduction part, transitions the logic state of the first transmission line to a second logic state. The second transmission line provides a predetermined signal to the data pad. The response element controls the second transmission line so that the second transmission line has the state of a verification result voltage for a misalignment state in response to the second logic state.

    摘要翻译： 针对准验证电路包括传感器焊盘，第一传输线，控制元件，数据焊盘，第二传输线和响应元件。 传感器垫包括绝缘部分和导电部分。 第一传输线电连接到导电部分和半导体器件的内部。 控制元件在第一逻辑状态下使第一传输线断言，并且在接收到导通部分的探测信号时，将第一传输线的逻辑状态转换到第二逻辑状态。 第二传输线向数据焊盘提供预定的信号。 响应元件控制第二传输线，使得第二传输线响应于第二逻辑状态具有用于不对准状态的验证结果电压的状态。

    Apparatus and method for signal bus line layout in semiconductor device
    130.
    发明申请
    Apparatus and method for signal bus line layout in semiconductor device 失效
    半导体器件中信号总线布线的装置和方法

    公开(公告)号：US20070238223A1

    公开(公告)日：2007-10-11

    申请号：US11809593

    申请日：2007-06-01

    申请人： Chang-Ho Lee ,  Jong-Hyun Choi

    发明人： Chang-Ho Lee ,  Jong-Hyun Choi

    IPC分类号： H01L21/00

    CPC分类号： H01L23/5286 ,  H01L24/06 ,  H01L2224/02166 ,  H01L2224/05554 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01024 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/14

    摘要： A device and method for layout and fabrication of power supply bus lines in an integrated circuit such as a memory circuit are described. In accordance with the present invention, power bus lines and bonding pads of the circuit are not necessarily formed in both edge regions and center regions of the device. The bonding pads are formed in the region according to the package being used, and the power bus lines are formed in the other region. This is accomplished by forming the bonding pads over landing pads. Landing pads are formed in both the center region and the edge region under the top surface of the device. If the device is to be packaged in an edge pad configuration, the bonding pads are formed over the landing pads in the edge region, and power supply bus lines can be formed over the landing pads in the center region. Similarly, if the device is to be packaged in a center pad configuration, the bonding pads are formed over the landing pads in the center region, and the power supply bus lines can be formed over the landing pads in the edge region. The bonding pads are connected to the landing pads by conductive vias. Because the power bus lines are not formed in the same region as bonding pads, they can occupy a relatively large portion of the region in which they are formed. That is, they can be made much larger than they would be using the conventional approach in which both bonding pads and power bus lines are formed in the same region. As a result, the power noise drawbacks of the conventional approach are eliminated.

    摘要翻译： 描述了诸如存储器电路的集成电路中的电源总线布线和制造的装置和方法。 根据本发明，电路的电源总线线路和接合焊盘不一定形成在器件的两个边缘区域和中心区域中。 接合焊盘形成在根据使用的封装的区域中，并且电力总线线路形成在另一区域中。 这通过在着陆垫上形成接合垫来实现。 着陆垫形成在装置的上表面下方的中心区域和边缘区域中。 如果将该器件封装在边缘焊盘配置中，则焊接区形成在边缘区域的着陆焊盘之上，并且电源总线可以形成在中心区域的着陆焊盘上。 类似地，如果要将器件封装在中心焊盘结构中，则接合焊盘形成在中心区域的着陆焊盘之上，并且电源总线可以形成在边缘区域的着陆焊盘上。 接合焊盘通过导电通孔连接到着陆焊盘。 由于电力总线线路不形成在与接合焊盘相同的区域中，所以它们可以占据其形成区域的较大部分。 也就是说，它们可以比使用在相同区域中形成接合焊盘和电力总线线路的常规方法大得多。 结果，消除了常规方法的功率噪声缺点。