公开(公告)号：US11450058B2

公开(公告)日：2022-09-20

申请号：US17028815

申请日：2020-09-22

Applicant: ATI Technologies ULC

Inventor： Guennadi Riguer

IPC: G06T15/06 ,  G06T15/08 ,  G06T17/20 ,  G06T17/10 ,  G06T15/00

Abstract: Techniques for performing ray tracing operations are provided. The techniques include receiving a request to determine whether a ray intersects any primitive of a set of primitives, evaluating the ray against non-leaf nodes of a bounding volume hierarchy to determine whether to eliminate portions of the bounding volume hierarchy from consideration, evaluating the ray against at least one early-termination node not eliminated from consideration, and determining whether to terminate traversal of the bounding volume hierarchy early and to identify that the ray hits a primitive, based on the result of the evaluation of the ray against the at least one early-termination node.

公开(公告)号：US11424761B2

公开(公告)日：2022-08-23

申请号：US17163879

申请日：2021-02-01

Applicant: ATI Technologies ULC

Inventor： Vinay Patel

IPC: H03M7/40 ,  H03M7/30

Abstract: An electronic device includes a decoding subsystem having a symbol decoder and a second symbol resolver with a plurality of local symbol decoders and a symbol selector. The symbol decoder outputs a first symbol decoded from an initial code for which a symbol is available in a block of the compressed data. The second symbol resolver decodes, in each local symbol decoder, substantially in parallel with decoding the first symbol in the symbol decoder, a respective symbol from a subsequent initial code for which a symbol is available in a respective sub-block of the block of the compressed data. The second symbol resolver outputs, by the symbol selector, as a second symbol, one of the respective symbols from the local symbol decoders selected by the symbol selector based on the initial code.

公开(公告)号：US11417295B2

公开(公告)日：2022-08-16

申请号：US17030676

申请日：2020-09-24

Applicant: ATI TECHNOLOGIES ULC

Inventor： David I. J. Glen

IPC: G09G3/20 ,  G09G5/36

Abstract: A graphics processing unit (GPU) includes a timing reference one or more processors configured to generate and provide, based on the timing reference, frames to a display system that supports variable refresh rates. The frames include a vertical blanking region having a first duration. The display system transmits information indicating an operation to be performed by the display system during the vertical blanking region of one or more subsequent frames. The one or more processors are configured to increase the first duration to a second duration in response to receiving the information indicating an operation to be performed by the display system during the vertical blanking region of at least one subsequent frame. In some cases, the first duration of the vertical blanking region is a minimum duration that corresponds to a maximum refresh rate supported by the display system.

公开(公告)号：US20220208145A1

公开(公告)日：2022-06-30

申请号：US17135346

申请日：2020-12-28

Applicant: ATI TECHNOLOGIES ULC

Inventor： David I. J. GLEN

IPC: G09G5/12 ,  G06F3/14

Abstract: A processing system synchronizes the display of a frame of video at an array of variable refresh rate (VRR) display modules of a display wall by dynamically adjusting a frequency and phase of the refresh rates of the VRR display modules via network protocols based on a selected master timing signal. The processing system selects a master timing signal and transmits the master timing signal to video processing units (VPUs) that render portions of the frame for display at the VRR display modules. Each VPU adjusts the frequency and phase of the VRR display modules for which it renders portions of the frame based on the master timing signal.

公开(公告)号：US20220206942A1

公开(公告)日：2022-06-30

申请号：US17135602

申请日：2020-12-28

Applicant: ATI Technologies ULC

Inventor： NIPPON RAVAL ,  PHILIP NG ,  ROSTISLAV S. DOBRIN

IPC: G06F12/06

Abstract: Methods, systems, and apparatuses provide support for multiple address spaces in order to facilitate data movement. One apparatus includes an input/output memory management unit (IOMMU) comprising: a plurality of memory-mapped input/output (MMIO) registers that map memory address spaces belonging to the IOMMU and at least a second IOMMU; and hardware control logic operative to: synchronize the plurality of MMIO registers of the at least the second IOMMU; receive, from a peripheral component endpoint coupled to the IOMMU, a direct memory access (DMA) request, the DMA request to a memory address space belonging to the at least the second IOMMU; access the plurality of MMIO registers of the IOMMU based on context data of the DMA request; and access, from the IOMMU, a function assigned to the memory address space belonging to the at least the second IOMMU based on the accessed plurality of MMIO registers.

公开(公告)号：US20220147366A1

公开(公告)日：2022-05-12

申请号：US17095904

申请日：2020-11-12

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Wentao Xu ,  Randall Alexander Brown ,  Vaibhav Amarayya Hiremath ,  Shijie Che ,  Kamraan Nasim

IPC: G06F9/4401

Abstract: In a system with a master processor and slave processors, sync points are used in boot instructions. While executing the boot instructions, the slave processor determines whether the sync point is enabled. In response to determining the sync point is enabled, the slave processor pauses execution of the boot instructions, waits for commands from the master processor, receives commands from the master processor, executes the received commands until a release command is received, and then continues to execute boot instructions. In response to determining the sync point is not enabled, the slave processor continues to execute boot instructions.

公开(公告)号：US11308648B2

公开(公告)日：2022-04-19

申请号：US17030048

申请日：2020-09-23

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Saurabh Sharma ,  Laurent Lefebvre ,  Sagar Shankar Bhandare ,  Ruijin Wu

IPC: G06T9/00 ,  G06T1/60

Abstract: Sampling circuitry independently accesses channels of texture data that represent a set of pixels. One or more processing units separately compress the channels of the texture data and store compressed data representative of the channels of the texture data for the set of pixels. The channels can include a red channel, a blue channel, and a green channel that represent color values of the set of pixels and an alpha channel that represents degrees of transparency of the set of pixels. Storing the compressed data can include writing the compress data to portions of a cache. The processing units can identify a subset of the set of pixels that share a value of a first channel of the plurality of channels and represent the value of the first channel over the subset of the set of pixels using information representing the value, the first channel, and boundaries of the subset.

公开(公告)号：US11307904B2

公开(公告)日：2022-04-19

申请号：US16224378

申请日：2018-12-18

Applicant: ATI TECHNOLOGIES ULC

Inventor： Michael McLean ,  Philip Ng

IPC: G06F9/50 ,  G06F9/4401 ,  G06F15/78

Abstract: A system-on-chip (SOC), includes a memory, a partition access module coupled to the memory, a partition requesting unit coupled to the partition access module, and a first input-output (IO) device coupled to the partition access module. The partition access module creates a first partition of the SOC. The first partition includes a first portion of a first processor, the first IO device, and a first portion of the memory. Based upon a partition request, the partition access module repartitions the SOC to create a dynamic partition. The dynamic partition includes the first portion of the first processor, the first input-output (IO) device, the first portion of the memory, and a second IO device not included in the first partition.

公开(公告)号：US20220101814A1

公开(公告)日：2022-03-31

申请号：US17119360

申请日：2020-12-11

Applicant: ATI Technologies ULC

Inventor： Nitant Patel ,  Parimalkumar Patel ,  Anthony Brown

IPC: G09G5/377 ,  G09G5/36 ,  G06F3/0482 ,  G06F3/0484 ,  G06F9/455

Abstract: Methods and apparatus provide a picture-in-picture (PIP) overlay window on a single physical monitor by displaying a first swap chain of the single physical monitor, reporting to an operating system (OS), a display level request for a fake connection to a non-existent second monitor, and displaying on the single physical monitor a virtual display defined by a second swap chain of the non-existent second monitor, as the PIP overlay window on the displayed content of the first swap chain on the single physical monitor.

公开(公告)号：US20220101563A1

公开(公告)日：2022-03-31

申请号：US17085851

申请日：2020-10-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Anthony Chan ,  Nooruddin Ahmed ,  Christopher J. Brennan ,  Bernard T. K. Chan

IPC: G06T9/00 ,  G06T15/00 ,  G06F17/15

Abstract: Systems, apparatuses, and methods for implementing automatic data format detection techniques are disclosed. A graphics engine receives data of indeterminate format and the graphics engine predicts an organization of the data. As part of the prediction, the graphics engine predicts the pixel depth (i.e., bytes per pixel (BPP)) and format separately. The graphics engine folds the data along pixel and channel boundaries to help in determining the pixel depth and format. The graphics engine scores modes against each other to generate different predictions for different formats. Then, the graphics engine generates scores for the predictions to determine which mode has a highest correlation with the input data. Next, the graphics engine chooses the format which attains the best score among the scores that were generated for the different modes. Then, the graphics engine compresses the unknown data using the chosen format with the best score.