公开(公告)号：US12046324B2

公开(公告)日：2024-07-23

申请号：US17861458

申请日：2022-07-11

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Harsh Rawat ,  Praveen Kumar Verma ,  Promod Kumar ,  Christophe Lecocq

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10 ,  G11C11/00

CPC classification number: G11C8/10 ,  G11C7/1087 ,  G11C7/222 ,  G11C8/08

Abstract: A memory circuit includes an array of memory cells arranged with first word lines connected to a first sub-array storing less significant bits of data and second word lines connected to a second sub-array storing more significant bits of data. A row decoder circuit coupled to the first and second word lines generates word line signals. A word line gating circuit is configured to selectively gate passage of the word line signals to the second word lines for the second sub-array in response to assertion of a maximum value signal. A data modification circuit performs a mathematical operation on data read from the array of memory cells, and asserts the maximum value signal if the mathematical operation performed on the less significant bits of data from the first sub-array produces a maximum data value.

公开(公告)号：US20240243945A1

公开(公告)日：2024-07-18

申请号：US18155094

申请日：2023-01-17

Applicant: STMicroelectronics International N.V.

Inventor： Avneep Kumar GOYAL ,  Nicolas GUION ,  Sumit Kumar SINGHAL ,  Jagtar SINGH ,  Dhulipalla Phaneendra KUMAR

IPC: H04L12/40

CPC classification number: H04L12/40143 ,  H04L2012/40215

Abstract: Apparatuses and computer-implemented methods for implementing a message-based protocol interface with a communication bus are provided. An example apparatus for implementing a message-based protocol interface with a communication bus may include message handler core circuitry having a transmit message buffer, wherein the transmit message buffer is configured to store a portion of a transmit message. The apparatus may further include receive handler circuitry configured to store a portion of a received message. The apparatus further includes a message handler processor comprising a processor and an instruction memory including program code, the instruction memory and program code configured to, with the processor, cause the message handler processor to transmit at least the portion of the transmit message from a transmit data memory to the message handler core circuitry and receive the received message from the receive handler circuitry into a receive data memory.

公开(公告)号：US20240243698A1

公开(公告)日：2024-07-18

申请号：US18409527

申请日：2024-01-10

Applicant: STMicroelectronics International N.V.

Inventor： Nunzio SPINA ,  Alessandro CASTORINA ,  Giuseppe PALMISANO

IPC: H03F1/02 ,  H03F3/45 ,  H03K5/24

CPC classification number: H03F1/0233 ,  H03F3/45475 ,  H03K5/24 ,  H03F2200/105

Abstract: An envelope detector receives a modulated signal and a differential stage coupled to the detector produces a replica modulated signal compared to produce a PWM-modulated signal having on and off times. A first switch is actuated to short-circuit the input to the envelope detector. A second switch is actuated to feed back to a storage capacitor a signal indicative of the difference between inputs to the differential stage. A third switch is actuated to short-circuit an input to the comparator. Logic circuitry activates the switched to implement offset compensation where: the first, second and third switches are actuated in the absence of the PWM-modulated signal during start-up and standby phases; and the first, second and third switches are actuated during off times of the PWM-modulated signal in a working phase alternating with the start-up/standby phases.

公开(公告)号：US12032747B1

公开(公告)日：2024-07-09

申请号：US18167500

申请日：2023-02-10

Applicant: STMicroelectronics International N.V.

Inventor： Stefano Paolo Rivolta ,  Roberto Mura ,  Edoardo Nagali

IPC: G06F3/01 ,  G01V8/00

CPC classification number: G06F3/017 ,  G01V8/005

Abstract: The present disclosure is directed to devices and methods for detecting dimming gestures using infrared detection. Infrared signals are detected using a thermal metal-oxide-semiconductor (TMOS) infrared (IR) sensor solution. The TMOS IR sensor is highly accurate and has low power consumptions compared to traditional IR sensors that utilize IR receivers.

公开(公告)号：US20240213153A1

公开(公告)日：2024-06-27

申请号：US18541497

申请日：2023-12-15

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics International N.V. ,  STMicroelectronics France

Inventor： Olivier Weber ,  Rohit Kumar Gupta ,  Eric Vandenbossche

IPC: H01L27/092 ,  H01L23/528 ,  H01L27/02

CPC classification number: H01L27/0928 ,  H01L23/528 ,  H01L27/0207

Abstract: An electronic device including a first active area of a first transistor, a first insulating region forming a first insulation of the first active area, a first insulating gate extending above the first active area and forming a second insulation of the first active area, and a first insulating gate contact coupled to the first insulating gate and positioned above both the first active area and the first insulating region, wherein the first insulating gate contact couples the first insulating gate to a power supply rail.

公开(公告)号：US12019118B2

公开(公告)日：2024-06-25

申请号：US18186549

申请日：2023-03-20

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics Application GmbH

Inventor： Roberto Colombo ,  Vivek Mohan Sharma ,  Samiksha Agarwal

IPC: G01R31/317

CPC classification number: G01R31/31703 ,  G01R31/31722

Abstract: In an embodiment a processing system includes a test circuit configured to set an address value, an upper address limit and a lower address limit to a given reference bit sequence, verify whether the upper-limit comparison signal has a respective third logic level and/or whether the lower-limit comparison signal has the respective third logic level, assert an error signal in response to determining that the upper-limit comparison signal does not have the respective third logic level or the lower-limit comparison signal does not have the respective third logic level, repeat a certain operation for each of the N bits.

公开(公告)号：US20240204663A1

公开(公告)日：2024-06-20

申请号：US18066765

申请日：2022-12-15

Applicant: STMicroelectronics International N.V.

Inventor： Antonino Torres

IPC: H02M3/157 ,  H02M1/08 ,  H02M1/36 ,  H02M3/158

CPC classification number: H02M3/157 ,  H02M1/08 ,  H02M1/36 ,  H02M3/158

Abstract: An integrated circuit device includes: a Buck converter; and a control circuit for the Buck converter, which includes: a comparator configured to compare a feedback voltage of the Buck converter with a reference voltage that increases from a first voltage to a second voltage; a pulse-width modulator configured to generate a pulse-width modulated (PWM) signal having a timing-varying pulse width proportional to the reference voltage; an AND gate configured to generate a first control signal by performing a logic AND operation on an output of the comparator and the PWM signal; a pulse generator configured to generate a second control signal by generating a pulse in response to a rising edge in the output of the comparator; and a selection circuit configured to, based on an output voltage of the Buck converter, select the first control signal or the second control signal as a control signal for the Buck converter.

公开(公告)号：US20240204127A1

公开(公告)日：2024-06-20

申请号：US18540625

申请日：2023-12-14

Applicant: STMicroelectronics International N.V.

Inventor： Antonin ZIMMER ,  Dominique GOLANSKI ,  Sebastien PLACE ,  Guillaume MARCHAND

IPC: H01L31/107 ,  H01L21/763 ,  H01L31/0288 ,  H01L31/18

CPC classification number: H01L31/107 ,  H01L21/763 ,  H01L31/0288 ,  H01L31/1804

Abstract: The present description concerns an avalanche photodiode comprising: a main PN junction adapted to being reverse-biased; and a plurality of semiconductor regions including at least: a first epitaxial semiconductor region of a first conductivity type; and a second semiconductor region of the second conductivity type, said second region being arranged to at least partially surround the first region, and comprising surfaces in contact with surfaces of said first region. The present description also concerns a method of manufacturing such a photodiode.

公开(公告)号：US20240194763A1

公开(公告)日：2024-06-13

申请号：US18523185

申请日：2023-11-29

Applicant: STMicroelectronics International N.V.

Inventor： Aurore CONSTANT ,  Ferdinando IUCOLANO ,  Cristina TRINGALI

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7786

Abstract: The present disclosure relates to a HEMT transistor comprising a first semiconductor layer, a gate arranged on a first surface of the first semiconductor layer, a first passivation layer made of a first material on the sides of the gate, the first passivation layer further extending over a first portion of said surface of the first semiconductor layer, and a second passivation layer made of a second material different from the first material on a second portion of said surface of the first semiconductor layer next to the first passivation layer.

公开(公告)号：US20240194570A1

公开(公告)日：2024-06-13

申请号：US18531010

申请日：2023-12-06

Applicant: STMicroelectronics International N.V.

Inventor： Mauro MAZZOLA

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49541 ,  H01L21/4842 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49503

Abstract: A common electrically conductive substrate includes substrate portions configured to host semiconductor chips. Adjacent substrate portions have mutually facing sides with elongate sacrificial connecting bars extending between the mutually facing sides. The electrically conductive substrate is cut along a length of the elongate sacrificial connecting bars to provide singulated individual substrate portions. The elongate sacrificial connecting bars are provided with an apertured structure comprising apertures distributed along the length of the elongate sacrificial connecting bars wherein the apertures provide zones of reduced resistance to cutting.