公开(公告)号：US11977463B2

公开(公告)日：2024-05-07

申请号：US17840785

申请日：2022-06-15

申请人： Kioxia Corporation

发明人： Kunihiko Suzuki

IPC分类号： G06F11/00 ,  G01R31/28 ,  G06F9/38 ,  G06F11/26 ,  G11C29/56

CPC分类号： G06F11/26 ,  G06F9/3861 ,  G01R31/2851 ,  G11C29/56

摘要： According to a certain embodiment, the semiconductor device includes: an integrated circuit unit; a command control unit configured to execute command control for the integrated circuit unit on the basis of a command, an address, and/or data, each supplied from an outside; an internal state control unit configured to detect an operating state inside the integrated circuit unit, and to provide an internal state signal indicating a first state or a second state in accordance with the detected operating state; and an instruction rejection control unit configured to instruct the internal state control unit to compulsorily turn the internal state signal to the first state if an operation of the integrated circuit unit has not been completed even after a predetermined maximum monitoring time has elapsed, and to instructs the command control unit to reject an input/output operation of the command, the address, and/or the data.

公开(公告)号：US20240143401A1

公开(公告)日：2024-05-02

申请号：US18404715

申请日：2024-01-04

申请人： Microsoft Technology Licensing, LLC

发明人： Prateek TANDON ,  Brian Jacob CORELL

IPC分类号： G06F9/50 ,  G06F9/38 ,  G06F9/48 ,  G06F13/362

CPC分类号： G06F9/5027 ,  G06F9/3836 ,  G06F9/4843 ,  G06F13/3625

摘要： A function processing service may receive a request to execute source code. The source code may include instructions to perform a function. The function processing service may determine whether at least one hardware acceleration condition has been satisfied for the function. If at least one hardware acceleration condition has been satisfied, the instructions in the source code may be translated into hardware-specific code corresponding to a hardware circuit. The hardware circuit may be configured based on the hardware-specific code, and the hardware circuit may perform the function. The function processing service may then provide the result obtained from the hardware circuit to the requesting entity.

公开(公告)号：US20240143330A1

公开(公告)日：2024-05-02

申请号：US17974314

申请日：2022-10-26

申请人： Nvidia Corporation

发明人： Michael Houston ,  Ryan Kelsey Albright ,  Benjamin Goska ,  Siddha Ganju ,  Elad Mentovich

IPC分类号： G06F9/38 ,  G06F1/26

CPC分类号： G06F9/3802 ,  G06F1/26

摘要： Systems and methods herein address power for one or more processing units, using one of a plurality of power profiles during execution of a group of real-time instructions, the one of the plurality of power profiles determined based in part on a relationship determined between the one of the plurality of power profiles and a power profile of the group of real-time instructions, the relationship limited by a threshold, and the plurality of power profiles are associated with a plurality of groups of reference instructions.

公开(公告)号：US11966742B2

公开(公告)日：2024-04-23

申请号：US18311810

申请日：2023-05-03

申请人： Intel Corporation

发明人： Eliezer Weissmann ,  Mark Charney ,  Michael Mishaeli ,  Robert Valentine ,  Itai Ravid ,  Jason W. Brandt ,  Gilbert Neiger ,  Baruch Chaikin ,  Efraim Rotem

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/30043 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/3836 ,  G06F9/3842

摘要： Systems, methods, and apparatuses relating to instructions to reset software thread runtime property histories in a hardware processor are described. In one embodiment, a hardware processor includes a hardware guide scheduler comprising a plurality of software thread runtime property histories; a decoder to decode a single instruction into a decoded single instruction, the single instruction having a field that identifies a model-specific register; and an execution circuit to execute the decoded single instruction to check that an enable bit of the model-specific register is set, and when the enable bit is set, to reset the plurality of software thread runtime property histories of the hardware guide scheduler.

公开(公告)号：US11966715B2

公开(公告)日：2024-04-23

申请号：US16939048

申请日：2020-07-26

申请人： Guobiao Zhang ,  Chen Shen

发明人： Guobiao Zhang ,  Chen Shen

IPC分类号： G06F7/57 ,  G06F7/544 ,  G06F9/30 ,  G06F9/38 ,  G06F16/901 ,  H10B41/27

CPC分类号： G06F7/57 ,  G06F7/544 ,  G06F9/3001 ,  G06F9/3877 ,  G06F16/9017 ,  H10B41/27

摘要： A three-dimensional processor (3D-processor) for parallel computing includes a plurality of computing elements. Each computing element comprises at least a three-dimensional memory (3D-M) array for storing at least a portion of a look-up table (LUT) for a mathematical function and an arithmetic logic circuit (ALC) for performing arithmetic operations on the LUT data. Deficiency in latency is offset by a large scale of parallelism.

公开(公告)号：US20240126613A1

公开(公告)日：2024-04-18

申请号：US17967740

申请日：2022-10-17

申请人： Intel Corporation

发明人： Saurabh GAYEN ,  Christopher J. HUGHES ,  Utkarsh Y. KAKAIYA ,  Alexander F. HEINECKE

IPC分类号： G06F9/50 ,  G06F9/355 ,  G06F9/38

CPC分类号： G06F9/505 ,  G06F9/3555 ,  G06F9/3877

摘要： A chip or other apparatus of an aspect includes a first accelerator and a second accelerator. The first accelerator has support for a chained accelerator operation. The first accelerator is to be controlled as part of the chained accelerator operation to access an input data from a source memory location in system memory, process the input data, and generate first intermediate data. The second accelerator also has support for the chained accelerator operation. The second accelerator is to be controlled as part of the chained accelerator operation to receive the first intermediate data, without the first intermediate data having been sent to the system memory, process the first intermediate data, and generate additional data. Other apparatus, methods, systems, and machine-readable medium are disclosed.

公开(公告)号：US20240126568A1

公开(公告)日：2024-04-18

申请号：US18572108

申请日：2022-08-02

申请人： Beijing Zitiao Network Technology Co., Ltd.

发明人： Shiman Shi ,  Mingxin Wei

IPC分类号： G06F9/448 ,  G06F9/38

CPC分类号： G06F9/448 ,  G06F9/3856

摘要： Embodiments of the present disclosure provide a method, apparatus, device, computer readable storage medium, electronic device, computer product and computer program for pattern rendering. The method comprises: obtaining a pattern rendering instruction, wherein the pattern rendering instruction comprises a plurality of coordinate points to be rendered and painting attributes corresponding to the coordinate points to be rendered; performing rendering operations on respective coordinate points to be rendered in a predetermined work to be rendered according to the painting attributes corresponding to the coordinate points to be rendered in the pattern rendering instruction; if a predetermined instruction is detected, sending the rendering operation to an external display terminal in real time so that the external display terminal displays the received rendering operation in real time.

公开(公告)号：US20240126557A1

公开(公告)日：2024-04-18

申请号：US17937101

申请日：2022-09-30

申请人： International Business Machines Corporation

发明人： Hayim SHAUL ,  Nir DRUCKER ,  Ehud AHARONI ,  Omri SOCEANU ,  Gilad EZOV

IPC分类号： G06F9/38 ,  G06F9/30 ,  H04L9/00

CPC分类号： G06F9/3887 ,  G06F9/30036 ,  H04L9/008

摘要： An example system includes a processor that can receive a number of complex packed tensors, wherein each of the complex packed tensors include real numbers encoded as imaginary parts of complex numbers. The processor can execute a single instruction, multiple data (SIMD) operation on the complex packed tensors using an integrated circuit of real and complex packed tensors in a complex domain to generate a result.

公开(公告)号：US20240126556A1

公开(公告)日：2024-04-18

申请号：US18469008

申请日：2023-09-18

申请人： SiFive, Inc.

发明人： Kathlene Rose Magnus

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3867 ,  G06F9/30036 ,  G06F9/3856

摘要： Apparatus and methods for vector instruction cracking after scalar dispatch are described. An integrated circuit includes a primary pipeline and a vector pipeline. The primary pipeline is configured to determine a type of instruction, responsive to a determination that the instruction is a vector instruction, create a reorder buffer entry in a reorder buffer for the vector instruction prior to out-of-order processing in the primary pipeline, and send the vector instruction to a vector pipeline. The vector pipeline is configured to process the vector instruction.

公开(公告)号：US11960934B2

公开(公告)日：2024-04-16

申请号：US17882898

申请日：2022-08-08

申请人： Neuralmagic Inc.

发明人： Alexander Matveev ,  Nir Shavit

IPC分类号： G06F9/50 ,  G06F9/38 ,  G06F9/54 ,  G06F12/084 ,  G06N3/04 ,  G06N3/045 ,  G06N3/08 ,  G06N3/084

CPC分类号： G06F9/5016 ,  G06F9/3877 ,  G06F9/544 ,  G06F12/084 ,  G06N3/04 ,  G06N3/045 ,  G06N3/08 ,  G06N3/084

摘要： A method and system for computing one or more outputs of a neural network having a plurality of layers is provided. The method and system can include determining a plurality of sub-computations from total computations of the neural network to execute in parallel wherein the computations to execute in parallel involve computations from multiple layers. The method and system also can also include avoiding repeating overlapped computations and/or multiple memory reads and writes during execution.