Abstract:
A low-pin-count chip package including a die pad for receiving a semiconductor chip and a plurality of connection pads electrically coupled to the semiconductor chip wherein the die pad and the connection pads have a concave profile. A package body is formed over the semiconductor chip, the die pad and the connection pads in a manner that a potion of the die pad and a portion of each connection pad extend outward from the bottom of the package body. The present invention further provides a novel method of producing the low-pin-count chip package described above.
Abstract:
An image surveillance system and an image surveillance method are provided. The image surveillance method includes following steps. An image is captured, and at least one reference target is defined in the captured image. A monitored object in the image is identified. A distance between the monitored object and each of the at least one reference target is individually calculated. Whether to announce at least one warning is determined according to a relationship between at least one threshold and the distance.
Abstract:
An image surveillance system and an image surveillance method are provided. The image surveillance method includes following steps. An image is captured, and at least one reference target is defined in the captured image. A monitored object in the image is identified. A distance between the monitored object and each of the at least one reference target is individually calculated. Whether to announce at least one warning is determined according to a relationship between at least one threshold and the distance.
Abstract:
A stacked-type solid electrolytic capacitor package structure includes a capacitor unit, a package unit and a conductive unit. The conductive unit includes a plurality of stacked-type capacitors stacked on top of one another and electrically connected with each other, and each stacked-type capacitor has a positive portion and a negative portion. The package unit includes a package body for enclosing the capacitor unit. The conductive unit includes a first conductive terminal and a second conductive terminal. The first conductive terminal has a first embedded portion electrically connected to the positive portion and enclosed by the package body and a first lateral exposed portion connected to the first embedded portion. The second conductive terminal has a second lateral exposed portion, a second front exposed portion, a second rear exposed portion, and a second embedded portion electrically connected to the negative portion and enclosed by the package body.
Abstract:
A thin heat pipe includes a thin hollow tube and a capillary structure. The capillary structure is formed in at least half of an inner wall of the thin hollow tube by a chemical etching process.
Abstract:
1,5-Dideoxy-1,5-imino-D-glucitol compounds as shown in the specification. Also disclosed is a method of treating a hexosaminidase-associated disease.
Abstract:
A method including providing a present wafer to be processed by a photolithography tool, selecting a processed wafer having a past chip design from a plurality of processed wafers, the processed wafer being previously processed by the photolithography tool, selecting a plurality of critical dimension (CD) data points extracted from a plurality of fields on the processed wafer, modeling the plurality of CD data points with a function relating CD to position on the processed wafer, creating a field layout on the present wafer for a new chip design, creating an initial exposure dose map for the new chip design using the function and the field layout, and controlling the exposure of the photolithography tool according to the initial exposure dose map to form the new chip design on the present wafer.
Abstract:
A heat pipe includes a step pipe, a mesh, and a supporting component. The step pipe has an evaporating section and two condensing sections. The condensing sections are on the two ends of the step pipe, respectively. The evaporating section lies between the two condensing sections. The inner spaces of the two condensing sections and the evaporating section are interconnected. The peripheral dimension of the evaporating section is larger than the peripheral dimension of each of the condensing sections. The mesh is contained in the step pipe and located inside the evaporating section and the condensing sections. The supporting component is contained in the step pipe and wrapped in the mesh. The combination of these structures increases air's flow rate inside the heat pipe and improves the heat pipe's heat conduction efficiency.
Abstract:
The present invention relates to a heat sink having juxtaposed heat pipes and a method for manufacturing the same. The heat sink includes a base, a plurality of heat pipes and a pair of side strips. The base has a surface on which an open trough and an insertion trough on both sides of the open trough are provided. Each heat pipe has an evaporating section. The evaporating sections are juxtaposed in the open trough and adhered to each other. Each evaporating section has a planar surface. The side strips are fixed into the insertion troughs and protrude from the surface of the base. The planar surface of each evaporating section and the outer surface of each side strip are coplanar. By this structure, the thermal contact surface between the heat pipes and electronic heat-generating sources is increased, so that the heat-dissipating efficiency of the heat sink is improved.
Abstract:
A solar cell includes a substrate, a lower conductor layer, an anti-reflection coating (ARC) layer and an upper conductor layer. The substrate has a front side, a back side and a doped region adjacent to the front side. The lower conductor layer has a first portion embedded into the doped region and a second portion other than the first portion. The ARC layer is disposed on the front side of the substrate and covers the lower conductor layer such that the second portion of the lower conductor layer is disposed in the ARC layer. The upper conductor layer has a first portion embedded into the ARC layer and a second portion other than the first portion of the upper conductor layer. The second portion of the upper conductor layer is exposed out of the ARC layer, and the upper conductor layer is electrically connected to the lower conductor layer.