公开(公告)号：US20080174923A1

公开(公告)日：2008-07-24

申请号：US11812221

申请日：2007-06-15

Applicant: Yi-Hsun Wu ,  Yan-Chih Jiang ,  Yu-Chang Lin ,  Jian-Hsing Lee

Inventor： Yi-Hsun Wu ,  Yan-Chih Jiang ,  Yu-Chang Lin ,  Jian-Hsing Lee

IPC: H02H9/00 ,  H01L21/336

CPC classification number: H01L27/0255

Abstract: A semiconductor device formed in a semiconductor substrate for dissipating electrostatic discharge and/or accumulated charge in an integrated circuit is provided. In one embodiment, the device comprises a semiconductor substrate; a plurality of layers of metal lines formed overlying the substrate; a plurality of via plugs through intermetal dielectric layers between the layers of metal lines and wherein the via plugs interconnect the metal lines; and a dummy pad formed over the plurality of layers of metal lines, the dummy pad having a diode connected thereto and to ground for providing a discharge path for the electrostatic discharge and/or accumulated charge.

公开(公告)号：US07384802B2

公开(公告)日：2008-06-10

申请号：US11438603

申请日：2006-05-22

Applicant: Jian-Hsing Lee ,  Yu-Chang Jong

Inventor： Jian-Hsing Lee ,  Yu-Chang Jong

IPC: H01L21/00

CPC classification number: H01L27/0259

Abstract: An electrostatic discharge (ESD) protection structure and a method for forming the same are provided. The structure includes a substrate having a buried layer, and a first and a second high-voltage well region on the buried layer. The first and second high-voltage well regions have opposite conductivity types and physically contact each other. The structure further includes a field region extending from the first high-voltage well region into the second high-voltage well region, a first doped region in the first high-voltage well region and physically contacting the field region, and a second doped region in the second high-voltage well region and physically contacting the field region. The first and second doped regions and the first high-voltage well region form a bipolar transistor that can protect an integrated circuit from ESD.

Abstract translation: 提供一种静电放电（ESD）保护结构及其形成方法。 该结构包括具有掩埋层的衬底以及掩埋层上的第一和第二高压阱区。 第一和第二高电压阱区具有相反的导电类型并且物理上彼此接触。 该结构还包括从第一高电压阱区域延伸到第二高电压阱区域的场区域，第一高压阱区域中的第一掺杂区域和与场区域物理接触的第二掺杂区域， 第二高压井区域并物理接触场区域。 第一和第二掺杂区域和第一高电压阱区域形成可以保护集成电路免受ESD的双极晶体管。

公开(公告)号：US20080055802A1

公开(公告)日：2008-03-06

申请号：US11509998

申请日：2006-08-26

Applicant: Chau-Neng Wu ,  Jian-Hsing Lee

Inventor： Chau-Neng Wu ,  Jian-Hsing Lee

IPC: H02H9/00

CPC classification number: H02H9/046

Abstract: An ESD protection circuit is implemented for a semiconductor device having a first circuit system operating with a first power supply voltage and a first complementary power supply voltage, and a second circuit system operating with a second power supply voltage and a second complementary power supply voltage. The ESD protection circuit includes a first diode having an anode coupled to the first power supply voltage and a cathode coupled to a first node connecting the first circuit system and the second circuit system for preventing a crosstalk of current between the first power supply voltage and the second complementary power supply voltage. A first MOS transistor module is coupled between the first node and the first complementary power supply for selectively creating a current path from the first node to the first complementary supply voltage for dissipating an ESD current during an ESD event.

公开(公告)号：US20070108527A1

公开(公告)日：2007-05-17

申请号：US11622574

申请日：2007-01-12

Applicant: Jian-Hsing Lee ,  Shui Chen

Inventor： Jian-Hsing Lee ,  Shui Chen

IPC: H01L23/62

CPC classification number: H01L27/0255

Abstract: The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of heavily doped P+ guard rings surrounding the I/O ESD protection device and the Vcc to Bss protection device. In addition, there is a heavily doped N+ guard ring surrounding the I/O protection device its P+ guard ring. The guard rings enhance structure diode elements providing enhanced ESD energy discharge path capability enabling the elimination of a specific conventional Vss to I/O pad ESD protection device. This reduces the capacitance seen by the I/O circuit while still providing adequate ESD protection for the active circuit devices.

Abstract translation: 本发明描述了一种用于提供具有降低的输入电容的ESD半导体保护的结构和工艺。 该结构由围绕I / O ESD保护器件和Vcc至Bss保护器件的重掺杂P +保护环组成。 另外，在I / O保护器件的P +保护环周围还有一个重掺杂的N +保护环。 保护环增强结构二极管元件，提供增强的ESD能量放电路径能力，从而能够消除特定的常规Vss至I / O焊盘ESD保护器件。 这降低了I / O电路所看到的电容，同时为有源电路器件提供足够的ESD保护。

公开(公告)号：US20060284256A1

公开(公告)日：2006-12-21

申请号：US11157200

申请日：2005-06-17

Applicant: Yi-Hsun Wu ,  Kuo-Feng Yu ,  Jian-Hsing Lee

Inventor： Yi-Hsun Wu ,  Kuo-Feng Yu ,  Jian-Hsing Lee

IPC: H01L23/62

CPC classification number: H01L27/0266

Abstract: The present invention provides a layout structure for an electrostatic discharge (ESD) protection circuit. The layout structure includes a first MOS device area, a second MOS device area, and a doped region. The first MOS device area has at least one source/drain region of a first polarity type. The second MOS device, which is adjacent to the first MOS device area, has at least one source/drain region of the first polarity type. A doped region of a second polarity type is interposed between the source/drain region of the first MOS device and the source/drain region of the second MOS device, such that the doped region and the source/drain regions interfacing therewith forming one or more diodes for dissipating ESD charges during an ESD event.

Abstract translation: 本发明提供了一种用于静电放电（ESD）保护电路的布局结构。 布局结构包括第一MOS器件区域，第二MOS器件区域和掺杂区域。 第一MOS器件区域具有至少一个第一极性类型的源极/漏极区域。 与第一MOS器件区域相邻的第二MOS器件具有至少一个第一极性类型的源极/漏极区域。 第二极性类型的掺杂区介于第一MOS器件的源极/漏极区域和第二MOS器件的源极/漏极区域之间，使得与其形成一个或多个的掺杂区域和源极/漏极区域 用于在ESD事件期间耗散ESD电荷的二极管。

公开(公告)号：US20060278928A1

公开(公告)日：2006-12-14

申请号：US11152440

申请日：2005-06-14

Applicant: Yi-Hsun Wu ,  Kuan-Lun Chang ,  Chuan-Ying Lee ,  Jian-Hsing Lee

Inventor： Yi-Hsun Wu ,  Kuan-Lun Chang ,  Chuan-Ying Lee ,  Jian-Hsing Lee

IPC: H01L23/62

CPC classification number: H01L27/0262

Abstract: A semiconductor layout structure for an electrostatic discharge (ESD) protection circuit is disclosed. The semiconductor layout structure includes a first area, in which one or more devices are constructed for functioning as a silicon controlled rectifier, and a second area, in which at least one device is constructed for functioning as a trigger source that provides a triggering current to trigger the silicon controlled rectifier for dissipating ESD charges during an ESD event. The first area and the second area are placed adjacent to one another without having a resistance area physically interposed or electrically connected therebetween, such that the triggering current received by the silicon controlled rectifier is increased during the ESD event.

Abstract translation: 公开了一种用于静电放电（ESD）保护电路的半导体布局结构。 半导体布局结构包括第一区域，其中构造一个或多个器件用作可控硅整流器，以及第二区域，其中构造至少一个器件用作触发源，该触发源提供触发电流 触发可控硅整流器，以在ESD事件期间耗散ESD电荷。 第一区域和第二区域彼此相邻放置，而不会在其间物理地插入或电连接电阻区域，使得在ESD事件期间由可控硅整流器接收的触发电流增加。

公开(公告)号：US20060268474A1

公开(公告)日：2006-11-30

申请号：US11137265

申请日：2005-05-25

Applicant: Shao-Chang Huang ,  Jian-Hsing Lee

Inventor： Shao-Chang Huang ,  Jian-Hsing Lee

IPC: H02H9/00

CPC classification number: H01L27/0251

Abstract: The present invention discloses a tie-off circuit coupled between a first potential and a gate of a MOS device whose source is connected to a second potential. The tie-off circuit includes at least one resistor and at least on diode. The resistor is coupled between the gate of the MOS device and the first potential for preventing the gate of the MOS device from floating during a normal circuit operation. The diode is coupled between the gate of the MOS device and the first potential, in parallel with the resistor, for reducing a voltage difference across a gate oxide layer of the MOS device during an electrostatic discharge (ESD) event, thereby protecting the same from ESD damage.

Abstract translation: 本发明公开了一种耦合在源极连接到第二电位的MOS器件的第一电位和栅极之间的断开电路。 连接电路至少包括一个电阻器，并且至少在二极管上。 电阻器耦合在MOS器件的栅极和用于防止MOS器件的栅极在正常电路操作期间浮置的第一电位之间。 二极管耦合在MOS器件的栅极和与电阻器并联的第一电位之间，用于在静电放电（ESD）事件期间减小MOS器件的栅氧化层上的电压差，从而保护 ESD损坏。

公开(公告)号：US06992361B2

公开(公告)日：2006-01-31

申请号：US10761658

申请日：2004-01-20

Applicant: Jiaw-Ren Shin ,  Jian-Hsing Lee ,  Shui-Hung Chen

Inventor： Jiaw-Ren Shin ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC: H01L29/00

CPC classification number: H01L27/0921 ,  H01L21/823892 ,  H01L27/0928

Abstract: A CMOS semiconductor product employs a first doped well of a first polarity and a second doped well of a second polarity opposite the first polarity, each formed laterally separated within a semiconductor substrate. The first doped well is further embedded within a third doped well of the second polarity that further separates the first doped well from the second doped well. The third doped well provides latch-up resistance for a pair of MOS transistors formed within the first doped well and the second doped well.

Abstract translation: CMOS半导体产品使用第一极性的第一掺杂阱和与第一极性相反的第二极性的第二掺杂阱，每个在半导体衬底内横向分离形成。 第一掺杂阱进一步嵌入在第二极性的第三掺杂阱中，其进一步将第一掺杂阱与第二掺杂阱分离。 第三掺杂阱为形成在第一掺杂阱和第二掺杂阱内的一对MOS晶体管提供闩锁电阻。

公开(公告)号：US20050280091A1

公开(公告)日：2005-12-22

申请号：US10887793

申请日：2004-07-09

Applicant: Shao-Chang Huang ,  Jian-Hsing Lee

Inventor： Shao-Chang Huang ,  Jian-Hsing Lee

IPC: H01L23/62 ,  H01L27/02 ,  H01L27/08 ,  H01L29/06

CPC classification number: H01L27/0255 ,  H01L27/0814 ,  H01L29/0619

Abstract: A semiconductor integrated circuit structure includes a plurality of diodes disposed in the substrate. These diodes are electrically coupled in series. At least one insertion region is disposed in the substrate between two of the diodes and a supply voltage node electrically coupled to the insertion region. Preferably, a guard ring surrounds the diodes.

Abstract translation: 半导体集成电路结构包括设置在基板中的多个二极管。 这些二极管串联电耦合。 至少一个插入区域设置在两个二极管之间的衬底中，以及电耦合到插入区域的电源电压节点。 优选地，保护环围绕二极管。

公开(公告)号：US20050275987A1

公开(公告)日：2005-12-15

申请号：US10867112

申请日：2004-06-14

Applicant: Yi-Hsun Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

Inventor： Yi-Hsun Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC: H01L27/02 ,  H02H3/20 ,  H03K17/0814

CPC classification number: H03K17/08142 ,  H01L27/0266

Abstract: An electrostatic discharge (ESD) protection circuit and method thereof are presented. In some embodiments, a high voltage tolerant input/output circuit comprises an ESD detection circuit, a first first-type transistor, a first second-type transistor, and a second second-type transistor. The first first-type transistor and the first second-type transistor are coupled to a pad. The ESD detection circuit determines whether ESD occurs at the pad and, if so, couples the gates of the first and second second-type transistors to the second power rail.

Abstract translation: 提出了一种静电放电（ESD）保护电路及其方法。 在一些实施例中，高耐压输入/输出电路包括ESD检测电路，第一第一型晶体管，第一第二型晶体管和第二第二型晶体管。 第一第一型晶体管和第一第二型晶体管耦合到焊盘。 ESD检测电路确定ESD是否发生在焊盘处，如果是，则将第一和第二第二型晶体管的栅极耦合到第二电源轨。