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    Memory device with fast write mode to mitigate power loss
    131.
    发明授权
    Memory device with fast write mode to mitigate power loss 有权

    公开(公告)号：US12254926B2

    公开(公告)日：2025-03-18

    申请号：US17817288

    申请日：2022-08-03

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung Lien ,  Juane Li ,  Sead Zildzic, Jr. ,  Zhenming Zhou

    IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34

    Abstract: Implementations described herein relate to a memory device with a fast write mode to mitigate power loss. In some implementations, the memory device may detect a condition associated with power supplied to the memory device. The memory device may detect one or more pending write operations to be performed to cause data to be written to memory cells of the memory device. The memory device may switch from a first voltage pattern, previously used by the memory device to write data to one or more memory cells of the memory device, to a second voltage pattern based on detecting the condition and based on detecting the one or more pending write operations. The memory device may perform at least one write operation, of the one or more pending write operations, using the second voltage pattern.

    Artificial neural network model selection
    132.
    发明授权
    Artificial neural network model selection 有权

    公开(公告)号：US12254401B2

    公开(公告)日：2025-03-18

    申请号：US17116847

    申请日：2020-12-09

    Applicant: Micron Technology, Inc.

    Inventor： Poorna Kale

    IPC: G06N3/08 ,  G06F18/21 ,  G06N3/045 ,  G06T7/00

    Abstract: A first artificial neural network (ANN) model implemented on a memory device can be executed on first data from an imaging device corresponding to a first image. A second ANN model implemented on the memory device can be executed on second data from the imaging device corresponding to a second, subsequent image. Whether an accuracy value of results yielded from the execution of the second ANN model on the second data is less than a threshold accuracy value can be determined by the memory device. Responsive to determining that the accuracy value is less than the threshold accuracy value, the first ANN model can be executed on third data from the imaging device corresponding to a third image subsequent to the second image. Such selection of ANN models can reduce excess power consumption of a memory device on which the ANN models are implemented.

    NITRIDE LATTICE SUPPORT IN MEMORY
    135.
    发明申请
    NITRIDE LATTICE SUPPORT IN MEMORY 有权

    公开(公告)号：US20250089233A1

    公开(公告)日：2025-03-13

    申请号：US18784176

    申请日：2024-07-25

    Applicant: Micron Technology, Inc.

    Inventor： Yongjun J. Hu

    IPC: H10B12/00

    Abstract: Systems, methods and apparatus are provided for nitride lattice support structures and double side capacitors in vertical three-dimensional (3D) memory. An example method includes a method for forming a nitride lattice support structures for an array of vertically stacked memory cells having access devices and storage nodes. The method includes depositing alternating layers of a channel material and a first sacrificial material in repeating iterations to form a vertical stack on a substrate. The vertical stack can be patterned to form a plurality of elongated vertical columns separated by a plurality of first vertical opening. A second sacrificial material can be deposited to fill the first vertical openings and cover the vertical stack. A plurality of vertical openings and lateral recesses can be formed. A nitride material can be deposited in the vertical openings and lateral recesses to form a plurality of nitride lattice support structures.

    CONROL LOOP CIRCUITRY
    136.
    发明申请
    CONROL LOOP CIRCUITRY 有权

    公开(公告)号：US20250088200A1

    公开(公告)日：2025-03-13

    申请号：US18958870

    申请日：2024-11-25

    Applicant: Micron Technology, Inc.

    Inventor： Steven J. Baumgartner ,  Neeraj Savla

    IPC: H03M1/78 ,  H03F3/45

    Abstract: Various embodiments of the present disclosure relate to apparatuses and methods for control loop circuitry. An interface circuit can comprise a digital to analog converter (DAC) configured to provide a differential output signal, a first control loop portion configured to receive a gain reference voltage and to output a first bias voltage to the DAC; and a second control loop portion configured to receive a common mode voltage of a differential input signal and to output a second bias voltage to the DAC.

    SELECTIVELY ERASING ONE OF MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING USING GATE INDUCED DRAIN LEAKAGE
    137.
    发明申请
    SELECTIVELY ERASING ONE OF MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING USING GATE INDUCED DRAIN LEAKAGE 有权

    公开(公告)号：US20250087275A1

    公开(公告)日：2025-03-13

    申请号：US18768970

    申请日：2024-07-10

    Applicant: Micron Technology, Inc.

    Inventor： Shyam Sunder Raghunathan ,  Yingda Dong ,  Akira Goda

    IPC: G11C16/16 ,  G11C16/04 ,  G11C16/28

    Abstract: An apparatus can comprise a memory array comprising a plurality of strings of memory cells. A first string of the plurality of strings can comprises: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller is coupled to the memory array and configured to, in order to selectively erase the second erase block independently of the first erase block: apply a voltage having a first value to a sense line coupled to the plurality of strings; apply a voltage having a second value less than the first value to the first group of access lines; and apply a voltage having a third value less than the second value to the second group of access lines.

    MULTIPLE TRANSISTOR ARCHITECTURE FOR THREE-DIMENSIONAL MEMORY ARRAYS
    138.
    发明申请
    MULTIPLE TRANSISTOR ARCHITECTURE FOR THREE-DIMENSIONAL MEMORY ARRAYS 有权

    公开(公告)号：US20250087266A1

    公开(公告)日：2025-03-13

    申请号：US18890171

    申请日：2024-09-19

    Applicant: Micron Technology, Inc.

    Inventor： Ferdinando Bedeschi

    IPC: G11C13/00 ,  G11C16/04 ,  H10B43/20

    Abstract: Methods, systems, and devices for multiple transistor architecture for three-dimensional memory arrays are described. A memory device may include conductive pillars coupled with an access line using two transistors positioned between the conductive pillar and the access line. As part of an access operation for a memory cell coupled with the conductive pillar, the memory device may be configured to bias the access line to a first voltage and activate the two transistors using a second voltage to couple the conductive pillar with the access line. Additionally, the memory device may be configured to bias a gate of a first transistor and a gate of a second transistor coupling an unselected conductive pillar with the access line to a third and fourth voltage, respectively, which may deactivate at least one of the first or second transistor during the access operation and isolate the unselected conductive pillar from the access line.

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