公开(公告)号：US07911856B2

公开(公告)日：2011-03-22

申请号：US12471411

申请日：2009-05-25

Applicant: Ming-Hsiu Lee ,  Yen-Hao Shih

Inventor： Ming-Hsiu Lee ,  Yen-Hao Shih

IPC: G11C7/00

CPC classification number: G11C13/0023 ,  G11C13/00 ,  G11C13/0004 ,  G11C17/06 ,  G11C17/16 ,  G11C2213/71 ,  G11C2213/77 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/1203 ,  H01L29/66833 ,  H01L29/792

Abstract: A method of accessing memory cells is disclosed. A first signal is sent to at least one layer select transistor. The at least one layer select transistor is activated based on the first signal. Signals are communicated to or from one or more memory cells based on the activated at least layer select transistor.

Abstract translation: 公开了访问存储器单元的方法。 第一信号被发送到至少一个层选择晶体管。 基于第一信号激活至少一个层选择晶体管。 基于激活的至少层选择晶体管将信号传送到或来自一个或多个存储器单元。

公开(公告)号：US07876608B2

公开(公告)日：2011-01-25

申请号：US12639789

申请日：2009-12-16

Applicant: Ming Hsiu Lee ,  Yi Chou Chen

Inventor： Ming Hsiu Lee ,  Yi Chou Chen

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2013/0092

Abstract: A method of programming a phase change device includes selecting a desired threshold voltage (Vth) and applying a programming pulse to a phase change material in the phase change device. The applying of the programming pulse includes applying a quantity of energy to the phase change material to drive at least a portion of this material above a melting energy level. A portion of the energy applied to the phase change material is allowed to dissipate below the melting energy level. The shape of the energy dissipation from the phase change material is controlled until the energy applied to the phase change material is less than a quenched energy level, to cause the phase change device to have the desired Vth. A remaining portion of the energy applied to the phase change material is allowed to dissipate to an environmental level.

Abstract translation: 编程相变装置的方法包括选择期望的阈值电压（Vth）并将编程脉冲施加到相变装置中的相变材料。 应用编程脉冲包括向相变材料施加一定量的能量以将该材料的至少一部分驱动在熔化能级以上。 施加到相变材料的能量的一部分被允许消散在熔融能级以下。 控制来自相变材料的能量耗散的形状，直到施加到相变材料的能量小于淬火能量水平，以使相变装置具有期望的Vth。 施加到相变材料的能量的剩余部分被允许消散到环境水平。

公开(公告)号：US07777275B2

公开(公告)日：2010-08-17

申请号：US11383973

申请日：2006-05-18

Applicant: Ming-Hsiu Lee

Inventor： Ming-Hsiu Lee

IPC: H01L27/12

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7881 ,  H01L29/792

Abstract: Methods which include providing a single crystal silicon substrate having a device pattern formed on a portion of the substrate where the device pattern has a protrusion, forming a protection layer on a portion of the protrusion, and forming an oxide insulation layer between the protrusion and the substrate using a thermal oxidation process; methods of forming a partial SOI structure which include providing a single crystal silicon substrate having a device pattern formed thereon where the device pattern comprises a non-SOI region and an SOI region having a protrusion, forming a protection layer on a portion of the protrusion, and forming an oxide insulation layer between the protrusion and the substrate using a thermal oxidation process; structures formed by such methods; and partial silicon-on-insulator structures comprising a single crystal silicon substrate having an device pattern disposed on a surface thereof where the device pattern includes a non-SOI region and an SOI region having a protrusion, and an oxide insulation layer disposed in the device pattern where a portion of the insulation layer is disposed under the protrusion such that the protrusion is isolated from the single crystal substrate, and where the non-SOI region is not isolated from the single crystal structure.

Abstract translation: 包括提供具有形成在基板的一部分上的器件图案的单晶硅衬底的方法，其中器件图案具有突起，在突起的一部分上形成保护层，并且在突出部和突起之间形成氧化物绝缘层 使用热氧化工艺的基板; 形成部分SOI结构的方法包括提供其上形成有器件图案的器件图案的单晶硅衬底，其中器件图案包括非SOI区域和具有突起的SOI区域，在突出部分的一部分上形成保护层， 以及使用热氧化工艺在所述突起和所述基板之间形成氧化物绝缘层; 通过这种方法形成的结构; 以及部分绝缘体上硅结构，其包括单晶硅衬底，其具有设置在其表面上的器件图案，其中器件图案包括非SOI区域和具有突起的SOI区域，以及设置在器件中的氧化物绝缘层 其中所述绝缘层的一部分设置在所述突起下方，使得所述突起与所述单晶基板隔离，并且其中所述非SOI区域不与所述单晶结构隔离。

公开(公告)号：US07773430B2

公开(公告)日：2010-08-10

申请号：US12314881

申请日：2008-12-18

Applicant: Chao-I Wu ,  Ming-Hsiu Lee ,  Tzu-Hsuan Hsu

Inventor： Chao-I Wu ,  Ming-Hsiu Lee ,  Tzu-Hsuan Hsu

IPC: G11C11/34

CPC classification number: G11C16/0475

Abstract: A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage (Vt) to a certain value; programming at least one of the first region and the second region of the PHINES cell by hot hole injection; and reading a logical state of the PHINES cell by measuring an output current of one of the first region and the second region; wherein different quantity of the output current is caused by interaction between different quantity of the hot hole stored in the first region and the second region, so as to determine the logical state of the PHINES cell by one-side reading scheme.

Abstract translation: 公开了一种识别单元中的逻辑信息的方法，特别是在通过单孔读取方案通过热空穴注入氮化物电子存储（PHINES）单元编程中的方法。 该方法包括以下步骤：通过将局部阈值电压（Vt）增加到一定值来擦除PHINES单元的第一区域和第二区域; 通过热空穴注入来编程PHINES单元的第一区域和第二区域中的至少一个; 以及通过测量所述第一区域和所述第二区域之一的输出电流来读取所述PHINES单元的逻辑状态; 其中，通过存储在第一区域和第二区域中的不同量的热孔之间的相互作用引起不同量的输出电流，以便通过单面读取方案确定PHINES单元的逻辑状态。

公开(公告)号：US20100110778A1

公开(公告)日：2010-05-06

申请号：US12266222

申请日：2008-11-06

Applicant: MING-HSIU LEE ,  MATTHEW J. BREITWISCH ,  CHUNG HON LAM

Inventor： MING-HSIU LEE ,  MATTHEW J. BREITWISCH ,  CHUNG HON LAM

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2013/0071 ,  G11C2013/009

Abstract: Memory devices and methods for operating such devices are described herein. A method as described herein includes applying a fixed sequence of voltage pulses across the memory cell of increasing pulse height to change the resistance state from the lower resistance state to the higher resistance state. The fixed sequence of voltage pulses cause increasing current through the phase change memory element until change to the higher resistance state occurs, and after the change the voltage pulses in the fixed sequence causing a voltage across the phase change memory element less than the threshold voltage.

Abstract translation: 这里描述了用于操作这样的设备的存储器件和方法。 本文所述的方法包括在增加脉冲高度的存储单元上施加固定的电压脉冲序列，以将电阻状态从较低电阻状态改变到较高电阻状态。 固定的电压脉冲序列导致增加的电流通过相变存储元件直到发生更高电阻状态的改变，并且在改变之后，固定序列中的电压脉冲导致相变存储元件上的电压小于阈值电压。

公开(公告)号：US20100008153A1

公开(公告)日：2010-01-14

申请号：US12561849

申请日：2009-09-17

Applicant: Hao-Ming Lien ,  Ming-Hsiu Lee

Inventor： Hao-Ming Lien ,  Ming-Hsiu Lee

IPC: G11C16/04

CPC classification number: G11C16/0466 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792

Abstract: A method for programming a mixed nonvolatile memory array having a plurality of mixed memory cells, wherein each mixed memory cell includes a depletion mode memory cell and an enhanced mode memory cell. The method comprises steps of programming the enhanced mode memory cell in a way of channel hot carrier and programming the depletion mode memory cell in a way of band-to-band tunneling hot carrier.

Abstract translation: 一种用于编程具有多个混合存储器单元的混合非易失性存储器阵列的方法，其中每个混合存储单元包括耗尽型存储单元和增强型存储单元。 该方法包括以通道热载波的方式对增强型存储器单元进行编程的步骤，并以带对带隧道热载波的方式对耗尽型存储单元进行编程。

公开(公告)号：US07608886B2

公开(公告)日：2009-10-27

申请号：US11327792

申请日：2006-01-06

Applicant: Tzu-Hsuan Hsu ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Ming-Chang Kuo

Inventor： Tzu-Hsuan Hsu ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Ming-Chang Kuo

IPC: H01L29/792

CPC classification number: H01L27/115 ,  G11C16/0475 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

Abstract: A memory array comprising vertical memory cells does not require any isolation layers between cells. Thus, a very compact, high density memory array can be achieved. Each memory cell in the memory array is configured to store 4 bits of data per cell. Multi level charge techniques can be used to increase the number of bit per cell and achieve further increased density for the memory array.

Abstract translation: 包括垂直存储单元的存储器阵列不需要单元之间的任何隔离层。 因此，可以实现非常紧凑，高密度的存储器阵列。 存储器阵列中的每个存储单元被配置为存储每个单元的4位数据。 可以使用多电平充电技术来增加每个电池的位数，并实现更高密度的存储器阵列。

公开(公告)号：US20080266932A1

公开(公告)日：2008-10-30

申请号：US11742090

申请日：2007-04-30

Applicant: Thomas Happ ,  Jan Boris Philipp ,  Ming-Hsiu Lee

Inventor： Thomas Happ ,  Jan Boris Philipp ,  Ming-Hsiu Lee

IPC: G11C11/00

CPC classification number: G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2213/79

Abstract: An integrated circuit includes a memory element configured to be programmed to any one of at least three resistance states and a circuit. The circuit is configured to program the memory element to a selected one of the at least three resistance states by applying a pulse to the memory element. The pulse includes one of at least three tail portions wherein each tail portion corresponds to one of the at least three resistance states.

Abstract translation: 集成电路包括被配置为被编程为至少三个电阻状态中的任一个的存储器元件和电路。 电路被配置为通过向存储元件施加脉冲将存储器元件编程为至少三个电阻状态中的所选择的一个。 脉冲包括至少三个尾部中的一个，其中每个尾部对应于至少三个电阻状态中的一个。

公开(公告)号：US07342264B2

公开(公告)日：2008-03-11

申请号：US11302738

申请日：2005-12-13

Applicant: Tzu-Hsuan Hsu ,  Chao-I Wu ,  Ming-Hsiu Lee

Inventor： Tzu-Hsuan Hsu ,  Chao-I Wu ,  Ming-Hsiu Lee

IPC: H01L29/80 ,  H01L29/76

CPC classification number: H01L21/28282 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/7923

Abstract: The invention is directed to a memory cell on a substrate having a plurality of shallow trench isolations form therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together define a vertical fin structure of the substrate. The memory cell comprises a straddle gate, a carrier trapping structure and at least two source/drain regions. The straddle gate is located on the substrate and straddles over the vertical fin structure. The carrier trapping structure is located between the straddle gate and the substrate, wherein the carrier trapping structure comprises a trapping layer directly in contact with the straddle gate and a tunnel layer located between the trapping layer and the substrate. The source/drain regions are located in a portion of the vertical fin structure of the substrate exposed by the straddle gate.

Abstract translation: 本发明涉及在其上形成有多个浅沟槽隔离物的衬底上的存储单元，其中浅沟槽隔离物的顶表面低于衬底的顶表面，并且浅沟槽隔离件一起限定垂直鳍状结构 底物。 存储单元包括跨门，载流子俘获结构和至少两个源/漏区。 跨门位于基板上，跨越垂直翅片结构。 载体捕获结构位于跨门和衬底之间，其中载流子俘获结构包括直接与跨骑门接触的捕获层和位于俘获层和基底之间的隧道层。 源极/漏极区域位于由跨门暴露的衬底的垂直鳍结构的一部分中。

公开(公告)号：US07266014B2

公开(公告)日：2007-09-04

申请号：US11161359

申请日：2005-08-01

Applicant: Chao-I Wu ,  Ming-Hsiu Lee

Inventor： Chao-I Wu ,  Ming-Hsiu Lee

IPC: G11C11/34

CPC classification number: G11C16/0475 ,  G11C16/18

Abstract: A method of operating a non-volatile memory is provided, wherein the non-volatile memory at least includes: a gate structure formed by stacking a tunneling dielectric layer, charge trapping layer, a dielectric layer and a gate conducting layer sequentially, and a source region and a drain region. When the operating method is carried out, a ultraviolet is irradiated to the non-volatile memory to inject electrons into the charge trapping layer to erase the non-volatile memory, and a negative voltage is applied to the gate conductive layer and a positive voltage is applied to the drain region to program the non-volatile memory by band-to-band induced hot hole injection.

Abstract translation: 提供了一种操作非易失性存储器的方法，其中非易失性存储器至少包括：通过层叠隧穿介电层，电荷俘获层，电介质层和栅极导电层顺序地形成的栅极结构，以及源极 区域和漏极区域。 当执行操作方法时，紫外线照射到非易失性存储器以将电子注入电荷捕获层以擦除非易失性存储器，并且向栅极导电层施加负电压，并且正电压为 施加到漏极区域以通过频带带诱导的热空穴注入对非易失性存储器进行编程。