公开(公告)号：US20220365552A1

公开(公告)日：2022-11-17

申请号：US17830163

申请日：2022-06-01

Applicant: Rambus Inc.

Inventor： Jun Kim ,  Pak Shing Chau ,  Wayne S. Richardson

IPC: G06F1/08 ,  H03L7/099 ,  H04L7/00 ,  H03L7/081 ,  H03L7/07 ,  H04L7/10 ,  G06F13/16 ,  G06F1/10

Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.

公开(公告)号：US11501848B2

公开(公告)日：2022-11-15

申请号：US17344155

申请日：2021-06-10

Applicant: Rambus Inc.

Inventor： Adrian E. Ong ,  Fan Ho

IPC: G11C29/04 ,  G11C29/00 ,  G11C29/44 ,  G11C29/48 ,  G11C11/401 ,  G11C29/12 ,  G11C11/408 ,  G11C29/02

Abstract: A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address.

公开(公告)号：US11500986B2

公开(公告)日：2022-11-15

申请号：US17028831

申请日：2020-09-22

Applicant: Rambus Inc.

Inventor： Simon Hoerder

IPC: G06F21/55

Abstract: A masked logic gate protected against side-channel attacks using Boolean masking with d+1 shares for each input variable, where d is an integer at least equal to 1 representing the protection order is described. The masked logic gate includes a first input configured to receive a number of shares yj (j=0, 1, 2 . . . ); a second input configured to receive (d+1)2 shares xi (i=0, 1, 2 . . . ) representative of an intermediate result output by one layer of a tree of gates implementing low-latency masking with a protection order of d; and a (d+1)-share output obtained by applying a logic function of the masked logic gate to the shares of the first and second inputs using domain-oriented masking.

公开(公告)号：US20220358989A1

公开(公告)日：2022-11-10

申请号：US17725026

申请日：2022-04-20

Applicant: Rambus Inc.

Inventor： Panduka Wijetunga ,  Aws Shallal ,  Joey M. Esteves

IPC: G11C11/4074

Abstract: A power-management integrated circuit (PMIC) is installed on a memory module to optimize power use among a collection of memory devices. The PMIC includes external power-supply nodes that receive relatively high and low supply voltages. Depending on availability, the PMIC uses one or both of these supply voltages to generate a managed supply voltage for powering the memory devices. The PMIC selects between operational modes for improved efficiency in dependence upon the availability of one or both externally provided supply voltages.

公开(公告)号：US11488018B1

公开(公告)日：2022-11-01

申请号：US16908024

申请日：2020-06-22

Applicant: Rambus Inc.

Inventor： Steven C. Woo

IPC: G06N3/08 ,  G06N3/04 ,  G06N3/063

Abstract: One or more neural network layers are implemented by respective sets of signed multiply-accumulate units that generate dual analog result signals indicative of positive and negative product accumulations, respectively. The two analog result signals and thus the positive and negative product accumulations are differentially combined to produce a merged analog output signal that constitutes the output of a neural node within the subject neural network layer.

公开(公告)号：US11487676B2

公开(公告)日：2022-11-01

申请号：US16953230

申请日：2020-11-19

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  James Tringali

IPC: G06F12/1036 ,  G06F12/02

Abstract: A memory system includes an address mapping circuit. The address mapping circuit receives an input memory address having a first set of address bits. The address mapping circuit applies a logic function to the input memory address to generate a mapped memory address. The logic function uses at least a subset of the first set of address bits in two separate operations that respectively determine two portions of the mapped memory address.

公开(公告)号：US20220343956A1

公开(公告)日：2022-10-27

申请号：US17705039

申请日：2022-03-25

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Bret Stott ,  Benedict C. Lau

IPC: G11C7/10 ,  G06F13/16 ,  G06F12/00

Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

公开(公告)号：US11474959B2

公开(公告)日：2022-10-18

申请号：US17228506

申请日：2021-04-12

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Craig E. Hampel

IPC: G06F13/16 ,  G11C7/10 ,  G11C5/04 ,  G11C11/4096 ,  G06F13/40 ,  G11C11/408 ,  G11C11/4093

Abstract: A memory module includes a substrate, plural memory devices, and a buffer. The plural memory devices are organized into at least one rank, each memory device having plural banks. The buffer includes a primary interface for communicating with a memory controller and a secondary interface coupled to the plural memory devices. For each bank of each rank of memory devices, the buffer includes data buffer circuitry and address buffer circuitry. The data buffer circuitry includes first storage to store write data transferred during a bank cycle interval (tRR). The address buffer circuitry includes second storage to store address information corresponding to the data stored in the first storage.

公开(公告)号：US20220327021A1

公开(公告)日：2022-10-13

申请号：US17734464

申请日：2022-05-02

Applicant: Rambus Inc.

Inventor： Michael Raymond MILLER ,  Stephen MAGEE ,  John Eric LINSTADT

IPC: G06F11/10 ,  G06F3/06

Abstract: Data and error correction information may involve accessing multiple data channels (e.g., 8) and one error detection and correction channel concurrently. This technique requires a total of N+1 row requests for each access, where N is the number of data channels (e.g., 8 data row accesses and 1 error detection and correction row access equals 9 row accesses.) A single (or at least less than N) data channel row may be accessed concurrently with a single error detection and correction row. This reduces the number of row requests to two (2)—one for the data and one for the error detection and correction information. Because, row requests consume power, reducing the number of row requests is more power efficient.

公开(公告)号：US11469927B2

公开(公告)日：2022-10-11

申请号：US17110530

申请日：2020-12-03

Applicant: Rambus Inc.

Inventor： Hae-Chang Lee ,  Brian S. Leibowitz ,  Jade M. Kizer ,  Thomas H. Greer ,  Akash Bansal

IPC: H04L25/03 ,  H04B1/12

Abstract: A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.