公开(公告)号：US20240313135A1

公开(公告)日：2024-09-19

申请号：US18623868

申请日：2024-04-01

Applicant: Rambus Inc.

Inventor： Yohan Frans ,  Simon Li ,  John Eric Linstadt ,  Jun Kim

IPC: H01L31/0236 ,  G06F3/06 ,  G06F12/00 ,  G06F12/02 ,  G06F13/16 ,  G06F13/372

CPC classification number: H01L31/02366 ,  G06F3/0613 ,  G06F3/0626 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F13/1684 ,  G06F13/372 ,  G06F12/00 ,  G06F13/16 ,  Y02D10/00

Abstract: A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.

公开(公告)号：US20220365552A1

公开(公告)日：2022-11-17

申请号：US17830163

申请日：2022-06-01

Applicant: Rambus Inc.

Inventor： Jun Kim ,  Pak Shing Chau ,  Wayne S. Richardson

IPC: G06F1/08 ,  H03L7/099 ,  H04L7/00 ,  H03L7/081 ,  H03L7/07 ,  H04L7/10 ,  G06F13/16 ,  G06F1/10

Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.

公开(公告)号：US11128388B2

公开(公告)日：2021-09-21

申请号：US16582448

申请日：2019-09-25

Applicant: Rambus Inc.

Inventor： Jun Kim ,  Wayne S. Richardson ,  Glenn Chiu

IPC: H04B17/11 ,  H04L5/14 ,  H04L25/03

Abstract: A method for calibrating a communication channel coupling first and second components includes transmitting a data signal from the first component to the second component on the communication channel, and sensing a characteristic, such as phase, of the data signal on the second component. Information about the sensed characteristic is fed back to the first component using an auxiliary channel. An adjustable parameter, such as phase, for the transmitter is adjusted on the first component in response to the information. Also, a characteristic of a data signal received from the transmitter on the second component is sensed and used to adjust an adjustable parameter for the receiver on the first component.

公开(公告)号：US11101393B2

公开(公告)日：2021-08-24

申请号：US16673431

申请日：2019-11-04

Applicant: Rambus Inc.

Inventor： Yohan Frans ,  Simon Li ,  John Eric Linstadt ,  Jun Kim

IPC: H01L31/0236 ,  G06F3/06 ,  G06F13/372 ,  G06F13/16 ,  G06F12/02 ,  G06F12/00

Abstract: A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.

公开(公告)号：US10468544B2

公开(公告)日：2019-11-05

申请号：US15369244

申请日：2016-12-05

Applicant: Rambus Inc.

Inventor： Yohan Frans ,  Simon Li ,  Eric Linstadt ,  Jun Kim

IPC: G06F12/02 ,  H01L31/0236 ,  G06F13/16 ,  G06F3/06 ,  G06F13/372 ,  G06F12/00

Abstract: A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.

公开(公告)号：US09568942B2

公开(公告)日：2017-02-14

申请号：US14961077

申请日：2015-12-07

Applicant: Rambus Inc.

Inventor： Jun Kim ,  Pak Shing Chau ,  Wayne S. Richardson

IPC: G06F1/00 ,  G06F1/08 ,  H03L7/099 ,  H04L7/00 ,  H03L7/081 ,  H03L7/07 ,  H04L7/10 ,  G06F13/16 ,  G06F1/10

CPC classification number: G06F1/08 ,  G06F1/10 ,  G06F13/1673 ,  G06F13/1689 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/0995 ,  H04L7/0008 ,  H04L7/0033 ,  H04L7/10 ,  Y02D10/14

Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.

Abstract translation: 一种存储器系统，其中通过测量在具有低于第一定时的频率的第二定时信号中出现的实际相位延迟来确定在存储器件中用于数据传输的第一定时信号的分配中将发生的定时漂移 并且分布在模拟第一定时信号的分布的至少一部分的漂移特性的一个或多个电路中。 实际的相位延迟在存储器件中确定并提供给存储器控制器，使得用于数据传输的定时信号的相位可以基于所确定的定时漂移来调整。

公开(公告)号：US20230409072A1

公开(公告)日：2023-12-21

申请号：US18206867

申请日：2023-06-07

Applicant: Rambus Inc.

Inventor： Jun Kim ,  Pak Shing Chau ,  Wayne S. Richardson

IPC: G06F1/08 ,  H03L7/099 ,  H04L7/00 ,  H03L7/081 ,  H03L7/07 ,  H04L7/10 ,  G06F13/16 ,  G06F1/10

CPC classification number: G06F1/08 ,  H03L7/0995 ,  H04L7/0008 ,  H03L7/0814 ,  H04L7/0033 ,  H03L7/07 ,  H04L7/10 ,  G06F13/1689 ,  G06F1/10 ,  G06F13/1673 ,  Y02D10/00

Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.

公开(公告)号：US11709525B2

公开(公告)日：2023-07-25

申请号：US17830163

申请日：2022-06-01

Applicant: Rambus Inc.

Inventor： Jun Kim ,  Pak Shing Chau ,  Wayne S. Richardson

IPC: G06F1/00 ,  G06F1/08 ,  H03L7/099 ,  H04L7/00 ,  H03L7/081 ,  H03L7/07 ,  H04L7/10 ,  G06F13/16 ,  G06F1/10

CPC classification number: G06F1/08 ,  G06F1/10 ,  G06F13/1673 ,  G06F13/1689 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/0995 ,  H04L7/0008 ,  H04L7/0033 ,  H04L7/10 ,  Y02D10/00

Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.

公开(公告)号：US20220077327A1

公开(公告)日：2022-03-10

申请号：US17445371

申请日：2021-08-18

Applicant: Rambus Inc.

Inventor： Yohan Frans ,  Simon Li ,  John Eric Linstadt ,  Jun Kim

IPC: H01L31/0236 ,  G06F12/02 ,  G06F13/16 ,  G06F3/06 ,  G06F13/372

Abstract: A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.

公开(公告)号：US20210173427A1

公开(公告)日：2021-06-10

申请号：US17102119

申请日：2020-11-23

Applicant: Rambus Inc.

Inventor： Jun Kim ,  Pak Shing Chau ,  Wayne S. Richardson

IPC: G06F1/08 ,  H03L7/099 ,  H04L7/00 ,  H03L7/081 ,  H03L7/07 ,  H04L7/10 ,  G06F13/16 ,  G06F1/10

Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.