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公开(公告)号：US10140958B2
公开(公告)日：2018-11-27
申请号：US15354434
申请日：2016-11-17
Inventor： Raphael Collado , Shivachitta S. Walishetty , Ling Yu Cheng
Abstract: Resources of multiple systems are managed in a computer device. A first processing system having a set of dedicated resources also has a resource manager to manage at least one of the resources. The first processing system is prevented from directly accessing the resources without authorization. A second processing system, connected to the set of dedicated resources, has a supervisor application to grant control to individual resources to the resource manager of the first processing system. A computer program is executed in the first processing system. The supervisor application grants control of at least one resource to the resource manager of the first processing system in a way that is transparently to the computer program executing in the first processing system.
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132.发明申请公开(公告)号：US20180329064A1
公开(公告)日：2018-11-15
申请号：US15590528
申请日：2017-05-09
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Pascal Mellot
CPC classification number: G01S17/36 , G01B11/25 , G01S17/06 , G01S17/89 , H04N5/2256
Abstract: A scanning emitter generates a transmit light signal at a first scan position, and a reflection of that transmit light signal is received at a sensor array including columns, wherein each column includes photosensitive pixels. Each photosensitive pixel in the sensor array generates a photo signal in response reception of the reflection of the transmit light signal. Over an evaluation time and for each individual column in the sensor array, a count is made as to the number of times the photosensitive pixels in the column generate photo signals. A light profile histogram is produced from the column counts. The light profile histogram is then processed to detect an optical misalignment between the scanning emitter and the sensor array.
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133.发明申请公开(公告)号：US20180309187A1
公开(公告)日：2018-10-25
申请号：US16017611
申请日：2018-06-25
Inventor： David Auchere , Laurent Marechal , Yvon Imbs , Laurent Schwarz
IPC: H01Q1/22 , H01L23/31 , H01L21/56 , H01L23/498 , H01L21/48 , H01L23/66 , H01L21/3105
Abstract: An electronic device includes a support plate having a mounting face and an electrical connection network. An integrated circuit chip is mounted on the mounting face and linked to the electrical connection network. An encapsulation block embeds the integrated circuit chip. An additional element made of an electrically conductive material is at least partly embedded within the encapsulation block. The additional conductive element has a main portion extending parallel to the support plate and has a secondary portion that is linked electrically to the integrated circuit chip. An opening is formed in the encapsulation block, and the secondary portion extends into that opening to make the electrical link. The additional conductive element may be an antenna.
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公开(公告)号：US20180270762A1
公开(公告)日：2018-09-20
申请号：US15692012
申请日：2017-08-31
Inventor： Michel Ayraud , Serge Ramet , Philippe Level
CPC classification number: H04W52/0274 , H03B5/1212 , H03B5/1278 , H03B21/025 , H03D7/166 , H03G3/3052 , H04B1/16 , H04B17/327 , Y02D70/00
Abstract: A local oscillator device includes an oscillator module including a first inductive element and a capacitive element coupled in parallel with the inductive element. A frequency divider is coupled to the oscillator module for delivering a local oscillator signal. The local oscillator device includes an autotransformer including the first inductive element and two second inductive elements respectively coupled to the terminals of the first inductive element and to two output terminals of the autotransformer, the output terminals being further coupled to input terminals of the frequency divider.
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公开(公告)号：US10073144B2
公开(公告)日：2018-09-11
申请号：US14494373
申请日：2014-09-23
Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS
Inventor： Christophe Lorin , Jean-Francois Garnier , Aurélien Mazard
IPC: G01R31/36
CPC classification number: G01R31/3842 , G01R31/3648 , G01R31/367
Abstract: A state of charge of a battery is estimated in several iterations, each iteration including: acquiring a measurement of intensity of current supplied by the battery, acquiring a measurement of voltage supplied by the battery, estimating a first state of charge of the battery based on a first estimated state of charge obtained upon a previous iteration and on the current intensity measurement, estimating a value of intensity of current supplied by the battery based on the voltage measurement and on a state of charge of the battery obtained upon the previous iteration, and calculating a corrected state of charge by adding to the first estimated state of charge a corrective term obtained by the product of a first correction gain multiplied by a factor representative of a difference between the estimated and measured current intensities.
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Patent Agency Ranking
公开(公告)号：US20180253404A1
公开(公告)日：2018-09-06
申请号：US15886353
申请日：2018-02-01
Applicant: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED , STMICROELECTRONICS (GRENOBLE 2) SAS
Inventor： John Kevin Moore , Sam Lee , Pascal Mellot , Donald Baxter , Stuart McLeod , Kenneth Dargan
CPC classification number: G06F17/18 , G01S7/4813 , G01S7/4863 , G01S7/4865 , G01S7/4876 , G01S7/497 , G01S17/10 , G06F11/0703
Abstract: A method includes receiving a histogram output from a detector sensor, and calculating a median point of a pulse waveform within the histogram. The pulse waveform has an even probability distribution over at least one quantization step of the histogram around the median point. A corresponding apparatus can include a detector sensor and a co-processor coupled to the detector sensor.
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公开(公告)号：US20180239384A1
公开(公告)日：2018-08-23
申请号：US15693214
申请日：2017-08-31
Inventor： Serge Ramet , Sandrine Nicolas , Danika Perrin , Cedric Rechatin
CPC classification number: G05F3/262 , G05F1/46 , H03F3/16 , H03F3/195 , H03F2200/294
Abstract: An integrated circuit includes a first stage configured to receive a bias current. A current regulation loop includes a transimpedance amplifier having a first transistor, and a second transistor having a gate coupled to a gate of the first transistor. The first transistor and the second transistor are configured to compare the bias current with a reference current, and to generate a regulation voltage on an output node of the transimpedance amplifier. A capacitor is coupled between the output node of the transimpedance amplifier and the gates of the first and second transistors.
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138.发明申请公开(公告)号：US20180205955A1
公开(公告)日：2018-07-19
申请号：US15691221
申请日：2017-08-30
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Mariano Bona , Fritz Lebowsky
IPC: H04N19/154 , H04N19/132 , H04N19/196 , H04N19/176 , H04N19/895 , H04N19/182
CPC classification number: H04N19/154 , H04N19/103 , H04N19/132 , H04N19/15 , H04N19/176 , H04N19/182 , H04N19/196 , H04N19/593 , H04N19/895
Abstract: A method is provided for encoding an initial digital signal as an encoded signal. The initial digital signal includes a sequence of samples representing a multidimensional space. Each sample is assigned at least one physical quantity. The method includes, for some of the current samples, localized encoding of the signal as encoded local digital signals. The encoded signal includes the encoded local digital signals. The method also includes an on-the-fly analysis of a characteristic associated with the encoded signal, and a direct or indirect adjustment at the sample level, of at least one encoding parameter involved in the localized encodings so as to stabilize the value of the characteristic on a target value to within a tolerance.
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公开(公告)号：US10019399B2
公开(公告)日：2018-07-10
申请号：US14940026
申请日：2015-11-12
Inventor： Daniele Mangano , Ignazio Antonino Urzi
IPC: G06F17/50 , G06F13/36 , H04L12/933 , G06F15/78 , H04L12/935 , G06F13/40
CPC classification number: G06F13/36 , G06F13/4068 , G06F15/7807 , G06F15/7825 , G06F17/5077 , G06F2217/04 , G06F2217/06 , H04L49/109 , H04L49/15 , H04L49/3009
Abstract: A system for designing Network-on-Chip interconnect arrangements includes a Network-on-Chip backbone with a plurality of backbone ports and a set of functional clusters of aggregated IPs providing respective sets of System-on-Chip functions. The functional clusters include respective sub-networks attachable to any of the backbone ports and to any other functional cluster in the set of functional clusters independently of the source map of the Network-on-Chip backbone.
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140.发明申请公开(公告)号：US20180190838A1
公开(公告)日：2018-07-05
申请号：US15689976
申请日：2017-08-29
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Karine Saxod , Alexandre Mas , Eric Saugier , Gaetan Lobascio , Benoit Besancon
IPC: H01L31/0203 , H01L31/18 , H01L31/0232 , H01L31/02 , H01L31/12 , B29C45/14
CPC classification number: H01L31/0203 , B29C45/14065 , B29C45/14639 , B29C45/14778 , B29K2995/0026 , B29L2031/3481 , H01L31/02002 , H01L31/02325 , H01L31/02327 , H01L31/12 , H01L31/18 , H01L33/483
Abstract: A cover for an electronic package is manufactured by placing an optical insert, having opposite faces and configured to allow light radiation to pass therethrough, between two opposite faces of a cavity of a mold in a position such that said optical faces of the optical insert make contact with said opposite faces of the cavity of the mold. A coating material is injected into the cavity and around the optical insert. The coating material is set to obtain a substrate that is overmolded around the optical insert so as to produce the cover. An electronic package includes an electronic chip mounted to a support substrate with the cover formed by the overmolded substrate mounted to the support substrate.
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