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    Bitcell Shifting Technique
    132.
    发明申请
    Bitcell Shifting Technique 审中-公开

    公开(公告)号：US20200342937A1

    公开(公告)日：2020-10-29

    申请号：US16397960

    申请日：2019-04-29

    Applicant: Arm Limited

    Inventor： Andy Wangkun Chen ,  Yew Keong Chong

    IPC: G11C11/419

    Abstract: Various implementations described herein are directed to circuitry having a bitcell array with bitcells arranged in columns and rows. The circuitry includes bitlines coupled to the columns of the bitcells and wordlines coupled to the rows of the bitcells. The bitcells are arranged in multiple groups of bitcells along corresponding wordlines in each row, and each group of bitcells in each row is configured to be shifted by at least one column with respect to another group of bitcells in a previous row.

    Apparatus and method to access a memory location
    133.
    发明授权
    Apparatus and method to access a memory location 有权

    公开(公告)号：US10817420B2

    公开(公告)日：2020-10-27

    申请号：US16175151

    申请日：2018-10-30

    Applicant: Arm Limited

    Inventor： Yew Keong Chong ,  Sriram Thyagarajan ,  Andy Wangkun Chen

    IPC: G06F12/06 ,  G06F12/02

    Abstract: A method for accessing two memory locations in two different memory arrays based on a single address string includes determining three sets of address bits. A first set of address bits are common to the addresses of wordlines that correspond to the memory locations in the two memory arrays. A second set of address bits concatenated with the first set of address bits provides the address of the wordline that corresponds to a first memory location in a first memory array. A third set of address bits concatenated with the first set of address bits provides the address of the wordline that corresponds to a second memory location in a second memory array. The method includes populating the single address string with the three sets of address bits and may be performed by an address data processing unit.

    Data compressor logic circuit
    134.
    发明授权
    Data compressor logic circuit 有权

    公开(公告)号：US10756753B2

    公开(公告)日：2020-08-25

    申请号：US16170723

    申请日：2018-10-25

    Applicant: Arm Limited

    Inventor： Shardendu Shekhar ,  Andy Wangkun Chen ,  Yew Keong Chong

    IPC: G06F7/50 ,  H03K19/21 ,  H03M7/00 ,  H03K19/20 ,  H03M7/30 ,  H03K19/0944

    Abstract: A compressor includes a logic circuit having transistors of a first channel type to receive a plurality of bit signals, and transistors of a second channel type, different from the first channel type, to receive the plurality of bit signals. The transistors of the first channel type are configured to generate an XOR logic output based on the plurality of bit signals, and the transistors of the second channel type are configured to generate, substantially simultaneous with the generation of the XOR logic output, an XNOR logic output based on the plurality of bit signals. The compressor includes NAND gates to receive multiplicand and multiplier bit signals.

    Apparatus and Method to Access a Memory Location
    135.
    发明申请
    Apparatus and Method to Access a Memory Location 审中-公开

    公开(公告)号：US20200133850A1

    公开(公告)日：2020-04-30

    申请号：US16175151

    申请日：2018-10-30

    Applicant: Arm Limited

    Inventor： Yew Keong Chong ,  Sriram Thyagarajan ,  Andy Wangkun Chen

    IPC: G06F12/06 ,  G06F12/02

    Abstract: A method for accessing two memory locations in two different memory arrays based on a single address string includes determining three sets of address bits. A first set of address bits are common to the addresses of wordlines that correspond to the memory locations in the two memory arrays. A second set of address bits concatenated with the first set of address bits provides the address of the wordline that corresponds to a first memory location in a first memory array. A third set of address bits concatenated with the first set of address bits provides the address of the wordline that corresponds to a second memory location in a second memory array. The method includes populating the single address string with the three sets of address bits and may be performed by an address data processing unit.

    Level shifter with bypass
    136.
    发明授权
    Level shifter with bypass 有权

    公开(公告)号：US10535386B2

    公开(公告)日：2020-01-14

    申请号：US15603252

    申请日：2017-05-23

    Applicant: ARM Limited

    Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Rahul Mathur ,  Abhishek Baradia ,  Hsin-Yu Chen

    IPC: G11C8/06 ,  G11C8/10

    Abstract: Various implementations described herein refer to an integrated circuit having level shifting circuitry and bypass switching circuitry. The level shifting circuitry is arranged for translating an input signal from a first voltage domain to an output signal for a second voltage domain. The bypass switching circuitry is arranged for activating and deactivating the level shifting circuitry based on a bypass control signal.

    Level Shifter with Bypass Control
    137.
    发明申请
    Level Shifter with Bypass Control 审中-公开

    公开(公告)号：US20190058475A1

    公开(公告)日：2019-02-21

    申请号：US15682327

    申请日：2017-08-21

    Applicant: ARM Limited

    Inventor： Andy Wangkun Chen ,  Cagla Cakir

    IPC: H03K19/0185 ,  H03K19/0944 ,  G11C5/14 ,  G11C7/10 ,  H03K3/356 ,  H03K17/16 ,  H03K3/0233

    Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include level shifting circuitry for translating an input signal from a first voltage domain to an output signal for a second voltage domain. The integrated circuit may include input logic circuitry for receiving multiple input signals and providing an inverted input signal to the level shifting circuitry based on the multiple input signals. The integrated circuit may include bypass switching circuitry for activating and deactivating the level shifting circuitry based on a bypass control signal and at least one of the multiple input signals.

    Low Power Input Gating
    140.
    发明申请
    Low Power Input Gating 有权
    低功率输入门控

    公开(公告)号：US20160343420A1

    公开(公告)日：2016-11-24

    申请号：US14849902

    申请日：2015-09-10

    Applicant: ARM Limited

    Inventor： Andy Wangkun Chen ,  Gus Yeung ,  Yew Keong Chong

    IPC: G11C8/18 ,  G11C8/06

    CPC classification number: G11C8/18 ,  G11C5/141 ,  G11C8/06

    Abstract: Various implementations described herein are directed to an integrated circuit for implementing low power input gating. In one implementation, the integrated circuit may include a chip enable device configured to receive and use a clock input signal to toggle a control input of memory based on a chip enable signal. The integrated circuit may include a latch device configured to latch the control input of the memory. The integrated circuit may include a latch enable device coupled between the chip enable device and the latch device. The latch enable device may be configured to receive the clock input signal from the chip enable device and use the clock input signal to gate the latch device based on a latch enable signal so as to selectively cutoff toggling of the clock input signal to the control input of the memory.

    Abstract translation: 本文所描述的各种实现涉及用于实现低功率输入门控的集成电路。 在一个实现中，集成电路可以包括芯片使能装置，其被配置为接收和使用时钟输入信号，以基于芯片使能信号切换存储器的控制输入。 集成电路可以包括被配置为锁存存储器的控制输入的锁存装置。 集成电路可以包括耦合在芯片使能装置和锁存装置之间的锁存使能装置。 锁存使能装置可以被配置为从芯片使能装置接收时钟输入信号，并且使用时钟输入信号基于锁存使能信号来对锁存器件进行门控，以便有选择地将时钟输入信号切换到控制输入 的记忆。

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