Hair trimmer with rotatable detented head
    132.
    发明申请
    Hair trimmer with rotatable detented head 有权
    头发修剪器与可旋转的止动头

    公开(公告)号:US20080155834A1

    公开(公告)日:2008-07-03

    申请号:US11648515

    申请日:2006-12-29

    CPC classification number: B26B19/04 B26B19/063 B26B19/3853 B26B19/386

    Abstract: A hair trimmer includes a handle having a housing including an actuation assembly rotatable relative to the housing, and a blade assembly including a reciprocating blade, a stationary blade and a blade assembly housing, the blade assembly constructed and arranged for being detachably engaged to the actuation assembly in a plane of rotation of the actuation assembly.

    Abstract translation: 一种修剪器包括具有壳体的手柄,该壳体包括可相对于壳体旋转的致动组件,以及包括往复式叶片,固定叶片和叶片组件壳体的叶片组件,所述叶片组件构造和布置成可拆卸地接合到致动器 组件在致动组件的旋转平面中。

    Inverter non-volatile memory cell and array system
    133.
    发明授权
    Inverter non-volatile memory cell and array system 有权
    逆变器非易失性存储单元和阵列系统

    公开(公告)号:US07257033B2

    公开(公告)日:2007-08-14

    申请号:US11084214

    申请日:2005-03-17

    CPC classification number: G11C16/10

    Abstract: NVM arrays include rows and columns of NVM cells comprising a floating gate, dual transistor, inverter storage element. Supply voltage for selected storage elements is turned off during a programming and an erase mode. Isolation transistors for each NVM cell or for each row of NVM cells may be used to control the supply voltage.

    Abstract translation: NVM阵列包括包括浮动栅极,双晶体管,逆变器存储元件的NVM单元的行和列。 在编程和擦除模式期间,所选存储元件的电源电压关闭。 可以使用每个NVM单元或每行NVM单元的隔离晶体管来控制电源电压。

    T cell immune response inhibitor
    134.
    发明申请
    T cell immune response inhibitor 审中-公开
    T细胞免疫应答抑制剂

    公开(公告)号:US20070184037A1

    公开(公告)日:2007-08-09

    申请号:US10590040

    申请日:2005-01-31

    CPC classification number: A61K39/00 A61K48/00 A61K2039/57

    Abstract: The present invention discloses a T-cell immune response inhibitor. The T-cell immune response inhibitor supplied in the present invention comprises a targeted pathogen nucleic acid vaccine and said nucleic acid vaccine's expression protein antigen; or it comprises a targeted pathogen nucleic acid vaccine and said nucleic acid vaccine expression protein antigen's active polypeptide; or it comprises the inactivated pathogen and targeted pathogen nucleic acid vaccine. The T-cell immune response inhibitor in the present invention is able to stimulate the organism to produce the normal specific antibody immune response and to suppress a specific cell's immune response, in particular the Th1 immune response, thus it may be effectively applied to treatment of autoimmune diseases, organ transplants, allergies and control of T-cell levels.

    Abstract translation: 本发明公开了一种T细胞免疫应答抑制剂。 本发明提供的T细胞免疫应答抑制剂包含靶向病原体核酸疫苗和所述核酸疫苗的表达蛋白质抗原; 或者其包含靶向病原体核酸疫苗和所述核酸疫苗表达蛋白抗原的活性多肽; 或者其包含灭活的病原体和靶向的病原体核酸疫苗。 本发明中的T细胞免疫应答抑制剂能够刺激生物体产生正常的特异性抗体免疫应答并抑制特定细胞的免疫应答,特别是Th1免疫应答,因此可有效地应用于治疗 自身免疫疾病,器官移植,过敏和T细胞水平的控制。

    Compact non-volatile memory cell and array system
    137.
    发明申请
    Compact non-volatile memory cell and array system 有权
    紧凑型非易失性存储单元和阵列系统

    公开(公告)号:US20060209597A1

    公开(公告)日:2006-09-21

    申请号:US11084213

    申请日:2005-03-17

    CPC classification number: G11C16/24

    Abstract: NVM arrays include rows and columns of NVM cells comprising a floating gate, a programming element, and a logic storage element. During a programming or erase mode, the floating gate of each cell is charged to a predetermined level. At the beginning of a read mode, all storage elements are pre-charged to a high supply voltage level. Following the pre-charge, selected cells are read to determine stored bit values. A charge status of the floating gate of each cell determines whether the storage element is turned on and the pre-charge voltage is pulled down corresponding to a bit value.

    Abstract translation: NVM阵列包括包括浮动栅极,编程元件和逻辑存储元件的NVM单元的行和列。 在编程或擦除模式期间,每个单元的浮置栅极被充电到预定的电平。 在读取模式开始时,所有存储元件都被预先充电到高电源电压。 在预充电之后,读取所选择的单元以确定存储的位值。 每个单元的浮动栅极的充电状态确定存储元件是否导通,并且预充电电压相应于位值被下拉。

    Compositions and methods for delivery of genetic material
    138.
    发明授权
    Compositions and methods for delivery of genetic material 有权
    用于遗传物质传递的组合物和方法

    公开(公告)号:US07001759B1

    公开(公告)日:2006-02-21

    申请号:US09359975

    申请日:1999-07-23

    Abstract: Methods of introducing genetic material into cells of an individual and compositions and kits for practicing the same are disclosed. The methods comprise the steps of contacting cells of an individual with a polynucleotide function enhancer and administering to the cells, a nucleic acid molecule that is free of retroviral particles. The nucleic acid molecule comprises a nucleotide sequence that encodes a protein that comprises at least one epitope that is identical or substantially similar to an epitope of a pathogen antigen or an antigen associated with a hyperproliferative or autoimmune disease, a protein otherwise missing from the individual due to a missing, non-functional, or partially functioning gene, or a protein that produces a therapeutic effect on an individual. Methods of prophylactically and therapeutically immunizing an individual against pathogens are disclosed. Pharmaceutical compositions and kits for practicing methods of the present invention are disclosed.

    Abstract translation: 公开了将遗传物质引入个体细胞的方法和用于实施其的组合物和试剂盒。 所述方法包括使个体的细胞与多核苷酸功能增强子接触并向细胞施用不含逆转录病毒颗粒的核酸分子的步骤。 核酸分子包含编码蛋白质的核苷酸序列,该蛋白质包含与病原体抗原或与过度增殖或自身免疫疾病相关的抗原的表位相同或基本相似的至少一个表位, 涉及一种缺失的,非功能的或部分功能的基因或对个体产生治疗作用的蛋白质。 公开了预防和治疗个体免受病原体的方法。 公开了用于本发明的实践方法的药物组合物和试剂盒。

    Native high-voltage n-channel LDMOSFET in standard logic CMOS
    139.
    发明申请
    Native high-voltage n-channel LDMOSFET in standard logic CMOS 有权
    标准逻辑CMOS中的原生高压n沟道LDMOSFET

    公开(公告)号:US20060001087A1

    公开(公告)日:2006-01-05

    申请号:US10884236

    申请日:2004-07-02

    Applicant: Bin Wang

    Inventor: Bin Wang

    CPC classification number: H01L29/4983 H01L29/4916 H01L29/7835

    Abstract: A native high-voltage n-channel LDMOSFET includes a p− doped substrate, a first n+ doped region disposed in the p− doped substrate, a source terminal coupled to the first n+ doped region, an n− well disposed in the substrate, a second n+ doped region disposed in the n− well, a drain terminal coupled to the second n+ doped region, a p+ doped region disposed in the substrate, a body terminal coupled to the p+ doped region, a dielectric layer disposed over the p− doped substrate and a portion of the n− well, a first trench disposed in the n− well, the trench filled with a dielectric material that is in contact with the dielectric layer, a second trench disposed at least partially in the n− well, the second trench filled with a dielectric material and isolating the second n+ region from the p+ region, and a gate partially or fully reversely doped with p+ implant (or an equivalent technique) and disposed over the dielectric layer and a portion of the first trench.

    Abstract translation: 原生高压n沟道LDMOSFET包括p掺杂衬底,设置在p掺杂衬底中的第一n +掺杂区,耦合到第一n +掺杂区的源极,设置在衬底中的n阱, 设置在n阱中的第二n +掺杂区域,耦合到第二n +掺杂区域的漏极端子,设置在衬底中的p +掺杂区域,耦合到p +掺杂区域的主体端子,设置在p掺杂区域上的介电层 衬底和n阱的一部分,设置在n阱中的第一沟槽,填充有与介电层接触的电介质材料的沟槽,至少部分地设置在n阱中的第二沟槽, 填充有电介质材料并且将第二n +区域与p +区域隔离的第二沟槽和部分地或完全地反向掺杂有p +注入(或等效技术)并且设置在电介质层和第一沟槽的一部分上的栅极。

    Graded-junction high-voltage MOSFET in standard logic CMOS
    140.
    发明申请
    Graded-junction high-voltage MOSFET in standard logic CMOS 有权
    分级结高压MOSFET在标准逻辑CMOS

    公开(公告)号:US20050236666A1

    公开(公告)日:2005-10-27

    申请号:US10884326

    申请日:2004-07-02

    Applicant: Bin Wang

    Inventor: Bin Wang

    CPC classification number: H01L29/7835 H01L29/0653 H01L29/1045 H01L29/42368

    Abstract: A high-voltage graded junction LDMOSFET includes a substrate of a first conductivity type, a well of the first conductivity type disposed in the substrate, a first region of a second conductivity type disposed in the well of the first conductivity type, a source terminal coupled to the first region of the second conductivity type, a well of the second conductivity type disposed in the substrate, a second region of the second conductivity type disposed in the well of the second conductivity type, a drain terminal coupled to the second region of the second conductivity type, a region of the first conductivity type disposed in the substrate, a body terminal coupled to the region of the first conductivity type, a graded-junction region formed of material of the first conductivity type separating the well of the first conductivity type and the well of the second conductivity type, the material of the first conductivity type in the graded-junction region doped at least an order of magnitude less than the wells, a dielectric layer disposed over the well of the first conductivity type, the graded-junction region and a portion of the well of the second conductivity type, a first isolator disposed in the well of the second conductivity type, the isolator including a dielectric material that is in contact with the dielectric layer, a second isolator disposed at least partially in the well of the second conductivity type, the second isolator including a dielectric material and isolating the second region of the second conductivity type from the region of the first conductivity type, and a gate disposed over the dielectric layer and a portion of the first isolator.

    Abstract translation: 高压梯度结LDMOSFET包括第一导电类型的衬底,设置在衬底中的第一导电类型的阱,设置在第一导电类型的阱中的第二导电类型的第一区域,源极端子耦合 到第二导电类型的第一区域,设置在基板中的第二导电类型的阱,设置在第二导电类型的阱中的第二导电类型的第二区域,耦合到第二导电类型的第二区域的漏极端子 第二导电类型,设置在基板中的第一导电类型的区域,耦合到第一导电类型的区域的主体端子,由第一导电类型的材料形成的分级接合区域,该第一导电类型的材料将第一导电类型的阱 和第二导电类型的阱,掺杂了至少一个数量级的渐变结区域中的第一导电类型的材料 小于所述阱的介质层,设置在所述第一导电类型的阱中的介电层,所述渐变接合区域和所述第二导电类型的阱的一部分,设置在所述第二导电类型的阱中的第一隔离器,所述隔离器 包括与电介质层接触的电介质材料,至少部分地设置在第二导电类型的阱中的第二隔离器,第二隔离器包括电介质材料,并将第二导电类型的第二区域与 第一导电类型和设置在电介质层上的栅极和第一隔离器的一部分。

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