公开(公告)号：US20060256892A1

公开(公告)日：2006-11-16

申请号：US11128905

申请日：2005-05-13

Applicant: Afshin Momtaz

Inventor： Afshin Momtaz

IPC: H04L25/06 ,  H04L25/10

CPC classification number: H04L25/061 ,  H04L7/033 ,  H04L25/03057

Abstract: An adaptive algorithm is implemented that optimizes the slicer threshold by optimizing the tail distribution of a “+1” and “−1” histogram. Through the use of a low resolution and under-sampled ADC, a histogram of received bit may be created. The difference between the y-intersects of lines derived from the “+1” and “−1” histogram is used to determine an error function. The algorithm iteratively updates the threshold value based on this error function.

Abstract translation: 实现了通过优化“+1”和“-1”直方图的尾部分布来优化限幅器阈值的自适应算法。 通过使用低分辨率和欠采样ADC，可以创建接收位的直方图。 使用从“+1”和“-1”直方图导出的线的y相交之间的差异来确定误差函数。 该算法基于该误差函数迭代地更新阈值。

公开(公告)号：US20060253746A1

公开(公告)日：2006-11-09

申请号：US11123355

申请日：2005-05-04

Applicant: Afshin Momtaz

Inventor： Afshin Momtaz

IPC: G06F11/00

CPC classification number: H03L7/0814 ,  H03L7/087 ,  H03L7/10 ,  H03M1/1245 ,  H04L7/0058 ,  H04L7/033 ,  H04L25/03146

Abstract: A system may adjust the times at which data is sampled by separate sampling mechanisms. Here, it may be desirable to ensure that one sampler samples data at substantially the same time as the other sampler. For example, output data from a high speed sampler that samples received data may be compared with an output of an analog to digital converter that samples the received data at a lower data rate. This difference or relative error may be accumulated over a period of time for given values of delay applied to the clock for the analog to digital converter. In this way, a delay value that minimizes the relative error may be selected as a desired delay value.

Abstract translation: 系统可以通过单独的采样机制来调整采样数据的时间。 在这里，可能需要确保一个采样器在与其他采样器基本相同的时间采样数据。 例如，可以将来自接收数据采样的高速采样器的输出数据与以较低数据速率对接收到的数据进行采样的模数转换器的输出进行比较。 对于给予模数转换器的时钟的延迟的给定值，该差异或相对误差可以在一段时间内累积。 以这种方式，可以将相对误差最小化的延迟值选择为期望的延迟值。

公开(公告)号：US20060244506A1

公开(公告)日：2006-11-02

申请号：US11117767

申请日：2005-04-28

Applicant: Namik Kocaman ,  Afshin Momtaz

Inventor： Namik Kocaman ,  Afshin Momtaz

IPC: H03L5/00

CPC classification number: H03K5/151 ,  H03K5/003 ,  H03K5/086

Abstract: A threshold adjustment circuit including: a current DAC for supplying or sinking a varying current; a differential pair of thin oxide transistors coupled to the DAC and coupled together at a common source node; a power supply for providing a supply voltage having a voltage level above reliability of the thin oxide transistors; and a third transistor for maintaining voltage of the common source node above a predetermined level and to disable the threshold adjustment circuit. The bulk and source of each of the differential pair thin oxide transistors is coupled to the common source node and each of the differential pair thin oxide transistors is switched by a signal to keep each of the differential pair thin oxide transistors in saturation region.

Abstract translation: 一种阈值调整电路，包括：用于提供或吸收变化电流的电流DAC; 耦合到DAC并在公共源节点处耦合在一起的薄氧化物晶体管的差分对; 用于提供具有高于薄氧化物晶体管的可靠性的电压电平的电源电压的电源; 以及第三晶体管，用于将公共源节点的电压维持在预定电平以上并禁止阈值调整电路。 每个差分对薄氧化物晶体管的体积和源极耦合到公共源节点，并且每个差分对薄氧化物晶体管被信号切换，以将每个差分对薄氧化物晶体管保持在饱和区域。

公开(公告)号：US06993106B1

公开(公告)日：2006-01-31

申请号：US09614308

申请日：2000-07-12

Applicant: Afshin Momtaz

Inventor： Afshin Momtaz

IPC: H03D3/24

CPC classification number: H03L7/107 ,  H03L7/189

Abstract: In a phase locked loop in which a phase detector compares an input signal to a reference signal and provides a difference signal to a charge pump or to a transconductance amplifier, a digital to analog converter is provided for connecting the output of the charge pump or transconductance amplifier to a voltage controlled oscillator whereby loop bandwidth can be increased from an operating value to an acquisition value for loop phase acquisition by changing the input to the DAC, thereby changing the amplification of the DAC.

Abstract translation: 在锁相环中，相位检测器将输入信号与参考信号进行比较，并向电荷泵或跨导放大器提供差分信号，提供数模转换器用于连接电荷泵或跨导的输出 放大器到压控振荡器，由此通过将输入改变为DAC，可以将环路带宽从工作值增加到环路相位采集的采集值，从而改变DAC的放大率。

公开(公告)号：US20050248396A1

公开(公告)日：2005-11-10

申请号：US10841766

申请日：2004-05-07

Applicant: Mario Caresosa ,  Afshin Momtaz ,  Guangming Yin

Inventor： Mario Caresosa ,  Afshin Momtaz ,  Guangming Yin

IPC: H03F3/45 ,  H03G1/00

CPC classification number: H03G1/007 ,  H03F3/45188 ,  H03F3/45197 ,  H03F2203/45504 ,  H03F2203/45638 ,  H03G1/0029 ,  H03G1/0088

Abstract: An input processing circuit includes a first and second input transistors for receiving a differential pair of first and second input signals, respectively. At least one resistor is coupled between first terminals of the first and second input transistors. The input processing circuit includes a variable gain amplifier (VGA) circuit. At least one first transistor has a gate terminal, and is coupled between the first terminals of the first and second input transistors. At least one second transistor has a gate terminal, and is coupled between the first terminals of the first and second input transistors. A gate switch is coupled to the gate terminal of the at least one second transistor. The at least one first transistor and the at least one second transistor adjust a gain of the input processing circuit in response to a control voltage. The control voltage is applied to the gate terminal of the at least one first transistor, and the control voltage is applied to the gate terminal of the at least one second transistor through the gate switch.

Abstract translation: 输入处理电路包括分别用于接收第一和第二输入信号的差分对的第一和第二输入晶体管。 至少一个电阻耦合在第一和第二输入晶体管的第一端之间。 输入处理电路包括可变增益放大器（VGA）电路。 至少一个第一晶体管具有栅极端子，并且耦合在第一和第二输入晶体管的第一端子之间。 至少一个第二晶体管具有栅极端子，并且耦合在第一和第二输入晶体管的第一端子之间。 栅极开关耦合到至少一个第二晶体管的栅极端子。 所述至少一个第一晶体管和所述至少一个第二晶体管响应于控制电压调整所述输入处理电路的增益。 控制电压被施加到至少一个第一晶体管的栅极端子，并且通过栅极开关将控制电压施加到至少一个第二晶体管的栅极端子。

公开(公告)号：US20050248382A1

公开(公告)日：2005-11-10

申请号：US10840524

申请日：2004-05-06

Applicant: David Chung ,  Afshin Momtaz ,  Mario Caresosa

Inventor： David Chung ,  Afshin Momtaz ,  Mario Caresosa

IPC: G06G7/12

CPC classification number: H03F3/4508 ,  H03F2200/456 ,  H03F2200/465 ,  H03F2203/45292 ,  H03F2203/45541

Abstract: A compensation apparatus maintains an effective resistance of one or more resistors in a circuit by associating an adjustable resistor circuit to each resistor. The compensation apparatus compares the resistance of a resistor in the circuit with the resistance of a reference resistor. When the resistance of the resistor in the circuit falls outside of a desired range, the compensation apparatus adjusts the resistance of the adjustable resistor to adjust the effective resistance of the resistor and adjustable resistor combination.

Abstract translation: 补偿装置通过将可调电阻器电路与每个电阻器相关联来保持电路中的一个或多个电阻器的有效电阻。 补偿装置将电路中的电阻器的电阻与参考电阻器的电阻进行比较。 当电路中的电阻电阻超出所需范围时，补偿装置调整可调电阻的电阻，调整电阻和可调电阻组合的有效电阻。

公开(公告)号：US06963220B2

公开(公告)日：2005-11-08

申请号：US10749965

申请日：2003-12-31

Applicant: Afshin Momtaz ,  Xin Wang ,  Jun Cao ,  Armond Hairapetian ,  David Chung

Inventor： Afshin Momtaz ,  Xin Wang ,  Jun Cao ,  Armond Hairapetian ,  David Chung

IPC: G06F5/10 ,  G11C7/00

CPC classification number: G06F5/10 ,  G06F2205/106

Abstract: Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.

Abstract translation: 用于实现高速先进先出（FIFO）结构的方法和电路。 在一个实施例中，公开了允许一个时钟（例如写时钟）的频率与另一（读取）时钟的频率不同的（例如，一半）的FIFO。 在另一个实施例中，呈现可以异步地设置和/或复位的FIFO。 公开了其他实施例，其中有效地监视读取和写入指针，以确保正确的时序关系，以检测时钟损耗以及检测其他异常FIFO条件。

公开(公告)号：US06940306B2

公开(公告)日：2005-09-06

申请号：US10750098

申请日：2003-12-31

Applicant: Afshin Momtaz ,  Xin Wang ,  Jun Cao ,  Armond Hairapetian ,  David Chung

Inventor： Afshin Momtaz ,  Xin Wang ,  Jun Cao ,  Armond Hairapetian ,  David Chung

IPC: G06F5/10 ,  G11C7/00

CPC classification number: G06F5/10 ,  G06F2205/106

Abstract: Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.

公开(公告)号：US20050134338A1

公开(公告)日：2005-06-23

申请号：US10776074

申请日：2004-02-11

Applicant: Afshin Momtaz

Inventor： Afshin Momtaz

IPC: H03D13/00

CPC classification number: H03D13/003

Abstract: A phase detector includes a first flip flop having a data input coupled to a first clock signal at a first frequency and a clock input coupled to a second clock signal at a second frequency. The frequency of the first clock signal is a multiple of the frequency of the second clock signal. The phase detector also includes a second flip flop having a data input coupled to an output of the first flip flop and a clock input coupled to the second clock signal.

Abstract translation: 相位检测器包括第一触发器，其具有耦合到第一频率的第一时钟信号的数据输入和以第二频率耦合到第二时钟信号的时钟输入。 第一时钟信号的频率是第二时钟信号的频率的倍数。 相位检测器还包括具有耦合到第一触发器的输出的数据输入和耦合到第二时钟信号的时钟输入的第二触发器。

公开(公告)号：US06725408B1

公开(公告)日：2004-04-20

申请号：US09632666

申请日：2000-08-07

Applicant: Jun Cao ,  Afshin Momtaz

Inventor： Jun Cao ,  Afshin Momtaz

IPC: G06F1100

CPC classification number: G01R31/31715 ,  H04B17/19 ,  H04B17/20

Abstract: A method and device for testing multi-channel transceivers in an integrated circuit is provided. More specifically, the present invention relates to a method and device for implementing a built-in self-test for multi-channel transceivers. An exemplaxy embodiment of the present invention includes a test pattern generator, a multiplexer, a demultiplexer, and a test result evaluator. The test pattern generator generates a test pattern which is fed into each of the input channels of the multiplexer. The multiplexer multiplexes the data from all its input channels and then relays the data to the demultiplexer. The test result evaluator then individually checks the data at each of the output channels of the demultiplexer to determine whether the data received at each output channel is the same as the test pattern. In order to facilitate the checking process, signature analysis is utilized.

Abstract translation: 提供了一种用于在集成电路中测试多通道收发器的方法和装置。 更具体地，本发明涉及一种用于实现多通道收发器的内置自检的方法和装置。 本发明的示例性实施例包括测试码型发生器，多路复用器，解复用器和测试结果评估器。 测试模式发生器产生一个测试模式，该测试模式被馈送到多路复用器的每个输入通道。 复用器复用来自其所有输入通道的数据，然后将数据中继到解复用器。 测试结果评估器然后单独地检查解复用器的每个输出通道上的数据，以确定在每个输出通道处接收的数据是否与测试模式相同。 为了便于检查过程，利用签名分析。