公开(公告)号：US07897468B1

公开(公告)日：2011-03-01

申请号：US12556604

申请日：2009-09-10

申请人： Zhijiong Luo ,  Qingqing Liang ,  Haizhou Yin ,  Huilong Zhu

发明人： Zhijiong Luo ,  Qingqing Liang ,  Haizhou Yin ,  Huilong Zhu

IPC分类号： H01L21/336

CPC分类号： H01L29/7833 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66484 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/7831 ,  H01L29/78648

摘要： A method of forming a dual gate semiconductor device is provided that includes providing a substrate having a first semiconductor layer and a second semiconductor layer, in which a first gate structure is formed on the second semiconductor layer. The second semiconductor layer and the first semiconductor layer are etched to expose the substrate using the first gate structure as an etch mask. A remaining portion of the first semiconductor layer is present underlying the first gate structure having edges aligned to the edges of the first gate structure. An epitaxial semiconductor material is formed on exposed portions of the substrate. The substrate and the remaining portion of the first semiconductor layer are removed to provide a recess having edges aligned to the edges of the first gate structure, and a second gate structure is formed in the recess. A method of forming a retrograded island is also provided.

摘要翻译： 提供一种形成双栅极半导体器件的方法，其包括提供具有第一半导体层和第二半导体层的衬底，其中在第二半导体层上形成第一栅极结构。 蚀刻第二半导体层和第一半导体层以使用第一栅极结构作为蚀刻掩模来露出衬底。 第一半导体层的剩余部分位于具有与第一栅极结构的边缘对准的边缘的第一栅极结构下方。 在衬底的暴露部分上形成外延半导体材料。 去除衬底和第一半导体层的剩余部分以提供具有与第一栅极结构的边缘对准的边缘的凹部，并且在凹部中形成第二栅极结构。 还提供了形成退火岛的方法。

公开(公告)号：US20100320503A1

公开(公告)日：2010-12-23

申请号：US12852995

申请日：2010-08-09

申请人： Yung Fu Chong ,  Zhijiong Luo ,  Judson Holt

发明人： Yung Fu Chong ,  Zhijiong Luo ,  Judson Holt

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66628 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636

摘要： The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. A strained channel CMOS transistor structure comprises a source stressor region comprising a source extension stressor region; and a drain stressor region comprising a drain extension stressor region; wherein a strained channel region is formed between the source extension stressor region and the drain extension stressor region, a width of said channel region being defined by adjacent ends of said extension stressor regions.

摘要翻译： 本发明涉及半导体集成电路。 更具体地但非唯一地，本发明涉及应变通道互补金属氧化物半导体（CMOS）晶体管结构及其制造方法。 应变通道CMOS晶体管结构包括源应力源区域，其包括源延伸应力区域; 和漏极应力区域，包括漏极延伸应力区域; 其中在所述源延伸应力区域和所述漏极延伸应力区域之间形成应变通道区域，所述沟道区域的宽度由所述延伸应力区域的相邻端限定。

公开(公告)号：US20100140674A1

公开(公告)日：2010-06-10

申请号：US12652275

申请日：2010-01-05

申请人： Zhijiong Luo ,  Huilong Zhu

发明人： Zhijiong Luo ,  Huilong Zhu

IPC分类号： H01L29/49 ,  H01L29/78

CPC分类号： H01L29/4975 ,  H01L21/28097 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/78

摘要： A field-effect transistor is provided. The field-effect transistor includes a gate structure including a fully silicided gate material overlying a gate dielectric disposed on a substrate, the fully silicided gate material having an upper region and a lower region, wherein the lower region has a first lateral dimension in accordance with a lateral dimension of the gate dielectric, and the upper region has a second lateral dimension different from the first lateral dimension.

摘要翻译： 提供场效应晶体管。 场效应晶体管包括栅极结构，其包括覆盖设置在衬底上的栅极电介质的完全硅化栅极材料，完全硅化的栅极材料具有上部区域和下部区域，其中下部区域具有根据 栅极电介质的横向尺寸，并且上部区域具有不同于第一横向尺寸的第二横向尺寸。

公开(公告)号：US07718513B2

公开(公告)日：2010-05-18

申请号：US11734888

申请日：2007-04-13

申请人： Huilong Zhu ,  Wenjuan Zhu ,  Zhijiong Luo

发明人： Huilong Zhu ,  Wenjuan Zhu ,  Zhijiong Luo

IPC分类号： H01L21/20

CPC分类号： H01L29/7833 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/76897 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659

摘要： Methods of forming silicided contacts self-aligned to a gate from polysilicon germanium and a structure so formed are disclosed. One embodiment of the method includes: forming a polysilicon germanium (poly SiGe) pedestal over a gate dielectric over a substrate; forming a poly SiGe layer over the poly SiGe pedestal, the poly SiGe layer having a thickness greater than the poly SiGe pedestal; doping the poly SiGe layer; simultaneously forming a gate and a contact to each side of the gate from the poly SiGe layer, the gate positioned over the poly SiGe pedestal; annealing to drive the dopant from the gate and the contacts into the substrate to form a source/drain region below the contacts; filling a space between the gate and the contacts; and forming silicide in the gate and the contacts.

摘要翻译： 公开了形成与多晶硅锗的栅极自对准的硅化物触点和如此形成的结构的方法。 该方法的一个实施例包括：在衬底上方的栅极电介质上形成多晶硅锗（poly SiGe）基座; 在所述多晶硅基底上形成多晶硅层，所述多晶SiGe层的厚度大于所述多晶SiGe基座; 掺杂多晶硅层; 同时从多晶硅层形成栅极和栅极的每一侧的接触，栅极位于多晶SiGe基座上方; 退火以将掺杂剂从栅极和触点驱动到衬底中以在触点下方形成源极/漏极区域; 填充门和触点之间的空间; 并在栅极和触点中形成硅化物。

公开(公告)号：US07666721B2

公开(公告)日：2010-02-23

申请号：US11308292

申请日：2006-03-15

申请人： Thomas W. Dyer ,  Zhijiong Luo ,  Haining S. Yang

发明人： Thomas W. Dyer ,  Zhijiong Luo ,  Haining S. Yang

IPC分类号： H01L21/00

CPC分类号： H01L29/0653 ,  H01L21/76243 ,  H01L21/76267 ,  H01L21/76283 ,  H01L21/823481 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

摘要： An improved semiconductor-on-insulator (SOI) substrate is provided, which contains a patterned buried insulator layer at varying depths. Specifically, the SOI substrate has a substantially planar upper surface and comprises: (1) first regions that do not contain any buried insulator, (2) second regions that contain first portions of the patterned buried insulator layer at a first depth (i.e., measured from the planar upper surface of the SOI substrate), and (3) third regions that contain second portions of the patterned buried insulator layer at a second depth, where the first depth is larger than the second depth. One or more field effect transistors (FETs) can be formed in the SOI substrate. For example, the FETs may comprise: channel regions in the first regions of the SOI substrate, source and drain regions in the second regions of the SOI substrate, and source/drain extension regions in the third regions of the SOI substrate.

摘要翻译： 提供了一种改进的绝缘体上半导体（SOI）衬底，其包含在不同深度处的图案化掩埋绝缘体层。 具体而言，SOI衬底具有基本平坦的上表面，并且包括：（1）不包含任何埋入绝缘体的第一区域，（2）第一区域，其包含第一深度处的图案化掩埋绝缘体层的第一部分 从SOI衬底的平坦的上表面），和（3）第二深度大于第二深度的第二深度上包含图案化的掩埋绝缘体层的第二部分的第三区域。 可以在SOI衬底中形成一个或多个场效应晶体管（FET）。 例如，FET可以包括：SOI衬底的第一区域中的沟道区域，SOI衬底的第二区域中的源极和漏极区域以及SOI衬底的第三区域中的源极/漏极延伸区域。

公开(公告)号：US07595233B2

公开(公告)日：2009-09-29

申请号：US11421510

申请日：2006-06-01

申请人： Zhijiong Luo ,  Yung Fu Chong ,  Huilong Zhu

发明人： Zhijiong Luo ,  Yung Fu Chong ,  Huilong Zhu

IPC分类号： H01L21/8238

CPC分类号： H01L29/7833 ,  H01L29/66507 ,  H01L29/7845

摘要： Methods of stressing a channel of a transistor as a result of a material volume change in a gate structure and a related structure are disclosed. In one embodiment, a method includes forming a gate over the channel, wherein the gate includes several materials, such as layers of silicon materials and a conducting material layer, above a gate dielectric, and is surrounded by a spacer, and then providing a volume change to some of the materials in the gate so that a stress is induced in the channel as a result of the volume change. A gate structure for a MOSFET structure may include a layer of silicon material over a gate dielectric and a first silicide and second silicide over the silicon material, where the first silicide induces a stress in a channel of the device. The first and second suicides may be separated by a layer of silicon material or in contact with each other.

摘要翻译： 公开了由于栅极结构的材料体积变化和相关结构而对晶体管的沟道施加应力的方法。 在一个实施例中，一种方法包括在通道上形成栅极，其中栅极包括若干材料，例如硅材料层和导电材料层，在栅极电介质上方，并被间隔物环绕，然后提供体积 改变为门中的一些材料，使得由于体积变化而在通道中引起应力。 用于MOSFET结构的栅极结构可以包括在栅极电介质上的硅材料层，以及硅材料上的第一硅化物和第二硅化物，其中第一硅化物在器件的沟道中引起应力。 第一和第二自杀剂可以被硅材料层分离或彼此接触。

公开(公告)号：US20090032845A1

公开(公告)日：2009-02-05

申请号：US11830972

申请日：2007-07-31

申请人： Huilong Zhu ,  Zhijiong Luo ,  Qingqing Liang

发明人： Huilong Zhu ,  Zhijiong Luo ,  Qingqing Liang

IPC分类号： H01L29/778 ,  H01L21/336

CPC分类号： H01L29/7843 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/205 ,  H01L29/26 ,  H01L29/267 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/7835 ,  H01L29/78654

摘要： A source trench and a drain trench are asymmetrically formed in a top semiconductor layer comprising a first semiconductor in a semiconductor substrate. A second semiconductor material having a narrower band gap than the first semiconductor material is deposited in the source trench and the drain trench to form a source side narrow band gap region and a drain side narrow band gap region, respectively. A gate spacer is formed and source and drain regions are formed in the top semiconductor layer. A portion of the boundary between an extended source region and an extended body region is formed in the source side narrow band gap region. Due to the narrower band gap of the second semiconductor material compared to the band gap of the first semiconductor material, charge formed in the extended body region is discharged through the source and floating body effects are reduced or eliminated.

摘要翻译： 源极沟槽和漏极沟槽在包括半导体衬底中的第一半导体的顶部半导体层中不对称地形成。 在源极沟槽和漏极沟槽中沉积具有比第一半导体材料窄的带隙的第二半导体材料，以分别形成源极窄带隙区域和漏极侧窄带隙区域。 形成栅极间隔物，并且在顶部半导体层中形成源区和漏极区。 扩展源极区域和延伸体区域之间的边界的一部分形成在源极窄带隙区域中。 由于与第一半导体材料的带隙相比，第二半导体材料的带隙较窄，所以形成在扩展体区域中的电荷通过源放电，并且减少或消除浮体效应。

公开(公告)号：US07485524B2

公开(公告)日：2009-02-03

申请号：US11425542

申请日：2006-06-21

申请人： Zhijiong Luo ,  Yung F. Chong ,  Judson R. Holt ,  Zhao Lun ,  Huilong Zhu

发明人： Zhijiong Luo ,  Yung F. Chong ,  Judson R. Holt ,  Zhao Lun ,  Huilong Zhu

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

摘要： The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices comprising source and drain (S/D) regions having slanted upper surfaces with respect to a substrate surface. Such S/D regions may comprise semiconductor structures that are epitaxially grown in surface recesses in a semiconductor substrate. The surface recesses preferable each has a bottom surface that is parallel to the substrate surface, which is oriented along one of a first set of equivalent crystal planes, and one or more sidewall surfaces that are oriented along a second, different set of equivalent crystal planes. The slanted upper surfaces of the S/D regions function to improve the stress profile in the channel region as well as to reduce contact resistance of the MOSFET. Such S/D regions with slanted upper surfaces can be readily formed by crystallographic etching of the semiconductor substrate, followed by epitaxial growth of a semiconductor material.

摘要翻译： 本发明涉及包括源极和漏极（S / D）区域的改进的金属氧化物半导体场效应晶体管（MOSFET）器件，其具有相对于衬底表面倾斜的上表面。 这样的S / D区域可以包括在半导体衬底中的表面凹槽中外延生长的半导体结构。 优选的表面凹部具有平行于基板表面的底表面，该底表面沿着第一组等效晶面中的一个取向，并且沿着第二不同组的等效晶面定向的一个或多个侧壁表面 。 S / D区域的倾斜上表面用于改善沟道区域中的应力分布以及降低MOSFET的接触电阻。 具有倾斜的上表面的这种S / D区域可以容易地通过半导体衬底的晶体蚀刻形成，随后半导体材料的外延生长。

公开(公告)号：US20080283962A1

公开(公告)日：2008-11-20

申请号：US11748521

申请日：2007-05-15

申请人： Thomas W. Dyer ,  Zhijiong Luo ,  Haining S. Yang

发明人： Thomas W. Dyer ,  Zhijiong Luo ,  Haining S. Yang

IPC分类号： H01L29/00 ,  H01L21/762

CPC分类号： H01L21/76229 ,  H01L21/3086 ,  H01L21/823878

摘要： A pedestal is formed out of the pad layer such that two edges of the pedestal coincide with a border of the wells as implanted. An extended pedestal is formed over the pedestal by depositing a conformal dielectric layer. The area of the extended pedestal is exposed the semiconductor surface below is recessed to a recess depth. Other trenches including at least one intra-well isolation trench are lithographically patterned. After a reactive ion etch, both an inter-well isolation trench and at least one intra-well isolation trench are formed. The width of the inter-well isolation trench may be reduced due to the deeper bottom surface compared to the prior art structures. The boundary between the p-well and the n-well below the inter-well isolation structure is self-aligned to the middle of the inter-well isolation structure.

摘要翻译： 从衬垫层形成基座，使得底座的两个边缘与植入的孔的边界重合。 通过沉积保形介电层在基座上形成延伸基座。 扩展基座的面积暴露在下方的半导体表面凹陷到凹陷深度。 包括至少一个井内隔离沟槽的其它沟槽被光刻图案化。 在反应离子蚀刻之后，形成阱间隔离沟槽和至少一个阱间隔离沟槽。 与现有技术的结构相比，由于较深的底面，间隙隔离沟槽的宽度可能会降低。 在井间隔离结构下面的p阱和n阱之间的边界与井间隔离结构的中间自对准。

公开(公告)号：US20080173946A1

公开(公告)日：2008-07-24

申请号：US11625984

申请日：2007-01-23

申请人： Huilong Zhu ,  Dae-Gyu Park ,  Zhijiong Luo ,  Ying Zhang

发明人： Huilong Zhu ,  Dae-Gyu Park ,  Zhijiong Luo ,  Ying Zhang

IPC分类号： H01L27/00 ,  H01L21/8238

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665

摘要： A CMOS structure and a method for fabricating the CMOS structure include a first transistor located within a first semiconductor substrate region having a first polarity. The first transistor includes a first gate electrode that includes a first metal containing material layer and a first silicon containing material layer located upon the first metal containing material layer. The CMOS structure also includes a second transistor located within a laterally separated second semiconductor substrate region having a second polarity that is different than the first polarity The second transistor includes a second gate electrode comprising a second metal containing material layer of a composition that is different than the first metal containing material layer, and a second silicon containing material layer located upon the second metal containing material layer. The first silicon containing material layer and the first semiconductor substrate region comprise different materials. The second silicon containing material layer and the second semiconductor substrate region also comprise different materials.

摘要翻译： CMOS结构和制造CMOS结构的方法包括位于具有第一极性的第一半导体衬底区域内的第一晶体管。 第一晶体管包括第一栅电极，其包括第一含金属材料层和位于第一含金属材料层上的第一含硅材料层。 CMOS结构还包括位于横向分离的第二半导体衬底区域内的第二晶体管，其具有与第一极性不同的第二极性。第二晶体管包括第二栅电极，第二栅电极包括不同于 第一含金属材料层和位于第二含金属材料层上的第二含硅材料层。 第一含硅材料层和第一半导体衬底区域包括不同的材料。 第二含硅材料层和第二半导体衬底区域也包括不同的材料。