公开(公告)号：US20220223195A1

公开(公告)日：2022-07-14

申请号：US17543932

申请日：2021-12-07

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi ,  Randall J. Rooney

IPC: G11C11/4078 ,  G06F13/16 ,  G06F21/55

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described in which waterfall attacks can be prevented from degrading data by alerting a memory controller that the memory device requests time to perform internal management operations, and should not be sent any further commands (e.g., activate commands) for a predetermined amount of time. In one embodiment, a memory device includes an external pin, a mode register, a memory array including a plurality of rows of memory cells, and circuitry configured to: determine that a criterion to perform an internal management operation on a subset of the plurality of rows has been met, transmit, in response to determining the criterion has been met, a signal to the external pin, determine a duration corresponding to the internal management operation, and write a bit value indicative of the determined duration to the mode register.

公开(公告)号：US20220069992A1

公开(公告)日：2022-03-03

申请号：US17003687

申请日：2020-08-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi

IPC: H04L9/08 ,  G06F11/10 ,  G06F3/06

Abstract: Apparatuses, systems, and methods for updating hash values in a memory. A memory device may include one or more hash circuits, each of which may generate a hash value based on an input, such as a row address, and a set of hash keys. To increase the unpredictability of operations in the memory, the hash keys may be changed responsive to one or more triggers. Example triggers may include, a power up/reset operation, a command issued to the memory, or internal logic of the memory (e.g., a timer). Responsive to one or more of these triggers, the hash keys may be regenerated. For example a new seed value may be generated and used by a random number generator to generate the new set of hash keys.

公开(公告)号：US20220068427A1

公开(公告)日：2022-03-03

申请号：US17003486

申请日：2020-08-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi

IPC: G11C29/44 ,  G11C29/42 ,  G11C29/18 ,  G11C29/12

Abstract: Apparatuses, systems, and methods for probabilistic data structures for error tracking. A memory device may include an error code correction (ECC) circuit which determines if data read from a memory array includes an error. If it does, the row address associated with the read data is provided to an error tracking circuit. The error tracking circuit may use probabilistic data structures, such as multiple count values, each indexed by different hash values of the row address. The count values may be used to determine if a given row address is repeatedly associated with errors. The memory may store these identified problem addresses in a data storage structure for example for diagnostic and/or repair purposes.

公开(公告)号：US20220068364A1

公开(公告)日：2022-03-03

申请号：US17412082

申请日：2021-08-25

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi

IPC: G11C11/406 ,  G11C11/4063

Abstract: Apparatuses, systems, and methods for reset of row hammer detector circuits. A row hammer detector circuit includes a hash circuit configured to store a hash key and provide a first count value based on a hash between the hash key and a row address corresponding to a row of memory cells of a memory array. The row hammer detector circuit is configured to provide a match signal in response to the count value exceeding a threshold to cause a targeted refresh of a victim row adjacent the row of memory cells. In response to exit from a self-refresh mode, the hash circuit is configured to update the stored hash key with a new hash key.

公开(公告)号：US20220036955A1

公开(公告)日：2022-02-03

申请号：US16944568

申请日：2020-07-31

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi

IPC: G11C16/12 ,  G11C16/26 ,  G11C16/04 ,  H03K19/0185 ,  H03K19/017

Abstract: Embodiments disclosed herein relate to level shifters of a memory device. Specifically, the level shifters include a first series arrangement of transistors to offset a first transistor. The level shifters also include a second series arrangement of transistors to offset a second transistor. The first series arrangement is opposite the second series arrangement. The output of the first series arrangement is coupled to a first pull-up transistor and configured to cut off a pull-up of the first pull-up transistor to a first voltage. The output of the second series arrangement is coupled to a second pull-up transistor and configured to cut off a pull-up of the second pull-up transistor to the first voltage. The first series arrangement and the second series arrangement are coupled to a second voltage at different times. The series arrangements of transistors enable faster level shifting over conventional level shifters.

公开(公告)号：US20210020223A1

公开(公告)日：2021-01-21

申请号：US16513400

申请日：2019-07-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi ,  Donald M. Morgan

IPC: G11C11/406 ,  G11C11/16 ,  G11C16/34 ,  G06F9/30

Abstract: Apparatuses and methods for tracking all row accesses in a memory device over time may be used to identify rows which are being hammered so that ‘victim’ rows may be identified and refreshed. A register stack may include a number of count values, each of which may track a number of accesses to a portion of the word lines of the memory device. Anytime a row within a given portion is accessed, the associated count value may be incremented. When a count value exceeds a first threshold, a second stack with a second number of count values may be used to track numbers of accesses to sub-portions of the given portion. When a second count value exceeds a second threshold, victim addresses may be provided to refresh the victim word lines associated with any of the word lines within the sub-portion.

公开(公告)号：US09405721B2

公开(公告)日：2016-08-02

申请号：US14297864

申请日：2014-06-06

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi ,  Don Morgan ,  Myung Gyoo Won

IPC: G06F13/42 ,  H03M13/05

CPC classification number: G06F13/4221 ,  H03M5/145 ,  H03M13/05 ,  H03M13/31

Abstract: Apparatuses and methods for performing a data bus inversion operation (DBI) are described. An example apparatus includes a DBI circuit configured to, in parallel, determine preliminary DBI bits based on a block of data. Individual preliminary DBI bits are associated with respective sub-blocks of the block of data. The DBI circuit is further configured to serially determine DBI bits based on the preliminary DBI bits. Individual ones of the DBI bits are associated with respective ones of the sub-blocks. The DBI circuit is further configured to invert bits of individual sub-blocks responsive to the respective associated DBI bits having a particular logical value to provide DBI data. The apparatus further includes data outputs configured to serially output sub-blocks of the DBI data and the DBI bits.

Abstract translation: 描述了用于执行数据总线反转操作（DBI）的装置和方法。 一个示例性设备包括一个DBI电路，被配置为并行地基于数据块来确定初始DBI位。 单独的初始DBI位与数据块的相应子块相关联。 DBI电路还被配置为基于初始DBI位串行确定DBI位。 DBI位中的各个与相应的子块相关联。 DBI电路还被配置为响应于具有特定逻辑值的相应的相关联的DBI位来反转各个子块的比特以提供DBI数据。 该装置还包括被配置为串行地输出DBI数据和DBI比特的子块的数据输出。

公开(公告)号：US09349491B1

公开(公告)日：2016-05-24

申请号：US14690150

申请日：2015-04-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Donald M. Morgan ,  Sujeet Ayyapureddi

IPC: G11C17/16 ,  G11C29/00

CPC classification number: G11C29/76 ,  G11C17/16 ,  G11C29/78 ,  G11C29/787 ,  G11C29/88

Abstract: Apparatus and methods for hybrid post package repair are disclosed. One such apparatus may include a package including memory cells and volatile memory. The volatile memory may be configured to store defective address data corresponding to a first portion of the memory cells that are deemed defective post-packaging. The apparatus may also include a decoder configured to select a second portion of the memory cells instead of the first portion of the memory cells when received current address data corresponding to an address to be accessed matches the defective address data stored in the volatile memory. The apparatus may also include non-volatile memory in the package. The apparatus may also include a mapping logic circuit in the package. The mapping logic circuit may be configured to program the replacement address data to the non-volatile memory subsequent to the defective address data being stored to the volatile memory.

Abstract translation: 公开了用于混合后包装修复的装置和方法。 一种这样的装置可以包括包括存储器单元和易失性存储器的封装。 易失性存储器可以被配置为存储对应于被认为是有缺陷的后封装的存储器单元的第一部分的有缺陷的地址数据。 该装置还可以包括解码器，其被配置为当与要访问的地址相对应的当前地址数据与存储在易失性存储器中的缺陷地址数据匹配时，选择存储器单元的第二部分而不是存储器单元的第一部分。 该装置还可以包括包装中的非易失性存储器。 该装置还可以包括封装中的映射逻辑电路。 映射逻辑电路可以被配置为在故障地址数据被存储到易失性存储器之后将替换地址数据编程到非易失性存储器。

公开(公告)号：US09213553B2

公开(公告)日：2015-12-15

申请号：US14046738

申请日：2013-10-04

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi ,  Raghukiran Sreeramaneni ,  Suryanarayana B. Tatapudi

IPC: H03K17/16 ,  G06F9/44 ,  G11C7/04 ,  G11C7/10

CPC classification number: G06F9/4411 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1096 ,  G11C2207/2254

Abstract: Driver systems and methods are provided, such as those that include identifying a process corner of a driver; and configuring the driver based on the identified process corner. Further embodiments provide a method that includes detecting a process corner of a driver, setting a reference voltage of a calibration circuit based on the process corner detected, and configuring the driver based on the reference voltage.

Abstract translation: 提供了驱动器系统和方法，例如包括识别驾驶员的过程角的那些; 并基于识别的过程角来配置驱动程序。 另外的实施例提供了一种方法，其包括检测驾驶员的过程角，基于检测到的过程角度来设置校准电路的参考电压，以及基于参考电压配置驾驶员。